1.25 MSPS, 16 mW Internal REF and CLK,
12-Bit Parallel ADC
AD7492
FUNCTIONAL BLOCK DIAGRAM
FEATURES
AV
DV
V
Specified for VDD of 2.7 V to 5.25 V
Throughput rate of 1 MSPS (AD7492)
Throughput rate of 1.25 MSPS (AD7492-5)
Throughput rate of 400 kSPS (AD7492-4)
Low power
DD
DD
20
DRIVE
21
REF OUT
5
4
2.5V
REF
CLOCK
OSCILLATOR
BUF
4 mW typ at 1 MSPS with 3 V supplies
11 mW typ at 1 MSPS with 5 V supplies
Wide input bandwidth
DB11
DB0
OUTPUT
DRIVERS
6
12-BIT SAR
ADC
T/H
V
IN
70 dB typ SNR at 100 kHz input frequency
2.5 V internal reference
On-chip CLK oscillator
Flexible power/throughput rate management
No pipeline delays
High speed parallel interface
Sleep mode: 50 nA typ
11
8
PS/FS
CS
CONTROL
LOGIC
10
CONVST
9
RD
AD7492
12
BUSY
7
19
DGND
24-lead SOIC and TSSOP packages
AGND
Figure 1.
GENERAL DESCRIPTION
FS
The type of sleep mode is hardware selected by the PS/ pin.
The AD7492, AD7492-4, and AD7492-5 are 12-bit high speed,
low power, successive approximation ADCs. The parts operate
from a single 2.7 V to 5.25 V power supply and feature
throughput rates up to 1.25 MSPS. They contain a low noise,
wide bandwidth track/hold amplifier that can handle
bandwidths up to 10 MHz.
Using these sleep modes allows very low power dissipation
numbers at lower throughput rates.
The analog input range for the part is 0 V to REFIN. The
2.5 V reference is supplied internally and is available for
external referencing. The conversion rate is determined by the
internal clock.
The conversion process and data acquisition are controlled
using standard control inputs allowing for easy interface to
microprocessors or DSPs. The input signal is sampled on the
PRODUCT HIGHLIGHTS
CONVST
falling edge of
and conversion is also initiated at this
1. High Throughput with Low Power Consumption. The
AD7492-5 offers 1.25 MSPS throughput with 16 mW
power consumption.
point. The BUSY pin goes high at the start of conversion and
goes low 880 ns (AD7492/AD7492-4) or 680 ns (AD7492-5)
later to indicate that the conversion is complete. There are no
pipeline delays associated with the part. The conversion result is
2. Flexible Power/Throughput Rate Management. The
conversion time is determined by an internal clock. The
part also features two sleep modes, partial and full, to
maximize power efficiency at lower throughput rates.
CS
RD
accessed via standard
parallel interface.
and
signals over a high speed
The AD7492 uses advanced design techniques to achieve very
low power dissipation at high throughput rates. With 5 V
supplies and 1.25 MSPS, the average current consumption
AD7492-5 is typically 2.75 mA. The part also offers flexible
power/throughput rate management.
3. No Pipeline Delay. The part features a standard successive
approximation ADC with accurate control of the sampling
CONVST
instant via a
control.
input and once-off conversion
4. Flexible Digital Interface. The VDRIVE feature controls the
voltage levels on the I/O digital pins.
It is also possible to operate the part in a full sleep mode and a
partial sleep mode, where the part wakes up to do a conversion
and automatically enters a sleep mode at the end of conversion.
5. Fewer Peripheral Components. The AD7492 optimizes
PCB space by using an internal reference and internal CLK.
Rev. A
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