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AD7478SRT-R2 PDF预览

AD7478SRT-R2

更新时间: 2024-12-01 12:41:39
品牌 Logo 应用领域
亚德诺 - ADI 转换器模数转换器光电二极管
页数 文件大小 规格书
20页 353K
描述
1 MSPS, 12-/10-/8-Bit ADCs in 6-Lead SOT-23

AD7478SRT-R2 数据手册

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1 MSPS, 12-/10-/8-Bit ADCs  
in 6-Lead SOT-23  
AD7476/AD7477/AD7478*  
FEATURES  
FUNCTIONAL BLOCK DIAGRAM  
Fast Throughput Rate: 1 MSPS  
Specified for VDD of 2.35 V to 5.25 V  
Low Power:  
V
DD  
3.6 mW Typ at 1 MSPS with 3 V Supplies  
15 mW Typ at 1 MSPS with 5 V Supplies  
Wide Input Bandwidth:  
8-/10-/12-BIT  
SUCCESSIVE-  
APPROXIMATION  
ADC  
V
T/H  
IN  
70 dB SNR at 100 kHz Input Frequency  
Flexible Power/Serial Clock Speed Management  
No Pipeline Delays  
High Speed Serial Interface  
SPI®/QSPI/MICROWIRE/DSP Compatible  
Standby Mode: 1 A Max  
SCLK  
SDATA  
CS  
CONTROL  
LOGIC  
6-Lead SOT-23 Package  
AD7476/AD7477/AD7478  
APPLICATIONS  
Battery-Powered Systems  
Personal Digital Assistants  
Medical Instruments  
GND  
Mobile Communications  
Instrumentation and Control Systems  
Data Acquisition Systems  
High Speed Modems  
Optical Sensors  
GENERAL DESCRIPTION  
PRODUCT HIGHLIGHTS  
The AD7476/AD7477/AD7478 are, respectively, 12-bit, 10-bit,  
and 8-bit, high speed, low power, successive-approximation  
ADCs. The parts operate from a single 2.35 V to 5.25 V power  
supply and feature throughput rates up to 1 MSPS. The parts  
contain a low noise, wide bandwidth track-and-hold amplifier  
that can handle input frequencies in excess of 6 MHz.  
1. First 12-/10-/8-Bit ADCs in a SOT-23 Package.  
2. High Throughput with Low Power Consumption.  
3. Flexible Power/Serial Clock Speed Management.  
The conversion rate is determined by the serial clock, allowing  
the conversion time to be reduced through the serial clock  
speed increase. This allows the average power consumption  
to be reduced while not converting. The part also features a  
shutdown mode to maximize power efficiency at lower  
throughput rates. Current consumption is 1 µA maximum  
when in shutdown.  
The conversion process and data acquisition are controlled  
using CS and the serial clock, allowing the devices to interface  
with microprocessors or DSPs. The input signal is sampled on  
the falling edge of CS and the conversion is also initiated at this  
point. There are no pipeline delays associated with the part.  
4. Reference Derived from the Power Supply.  
The AD7476/AD7477/AD7478 use advanced design techniques  
to achieve very low power dissipation at high throughput rates.  
5. No Pipeline Delay.  
The parts feature a standard successive-approximation ADC  
with accurate control of the sampling instant via a CS input  
and once-off conversion control.  
The reference for the part is taken internally from VDD. This  
allows the widest dynamic input range to the ADC. Thus the  
analog input range for the part is 0 V to VDD. The conversion  
rate is determined by the SCLK.  
*Protected by U.S.Patent No. 6,681,332.  
REV. D  
Information furnished by Analog Devices is believed to be accurate and  
reliable. However, no responsibility is assumed by Analog Devices for its  
use, norforanyinfringementsofpatentsorotherrightsofthirdpartiesthat  
may result from its use. No license is granted by implication or otherwise  
under any patent or patent rights of Analog Devices. Trademarks and  
registered trademarks are the property of their respective owners.  
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.  
Tel: 781/329-4700  
Fax: 781/326-8703  
www.analog.com  
© 2004 Analog Devices, Inc. All rights reserved.  

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