PRELIMINARY TECHNICAL DATA
Pseudo Differential, 600kSPS,
a
PreliminaryTechnicalData
12- & 10-Bit ADCs in 8-lead SOT-23
AD7453/AD7443
FEATU RES
F U NC T IO NAL B LO C K D IAG RAM
Specified for VDD of 2.7 V to 5.25 V
Lo w Po w e r a t m a x Th ro u g h p u t Ra t e :
3.75 m W typ at 1MSPS w ith VDD = 3 V
9 m W typ at 1MSPS w ith VDD = 5 V
Ps e u d o Diffe re n t ia l An a lo g In p u t
Wide Input Bandw idth:
V
DD
V
V
12-BIT SUCCESSIVE
APPROXIMATION
ADC
IN+
70d B S INAD a t 100kHz In p u t Fre q u e n cy
Flexible Pow er/ Serial Clock Speed Managem ent
No Pipeline Delays
T/H
IN-
V
REF
Hig h S p e e d S e ria l In t e rfa ce - S PITM/ QS PITM
/
MICROWIRETM
/ DS P Co m p a t ib le
Po w e r-Do w n Mo d e : 1µA m a x
8 Pin S OT-23 a n d µS OIC Pa cka g e s
SCLK
SDATA
CS
CONTROL
LOGIC
AP P LICATIO N S
AD7453/
AD7443
Tra n s d u c e r In t e rfa c e
Battery Pow ered System s
Data Acquisition System s
Portable Instrum entation
Motor Control
Co m m u n ic a t io n s
GND
G E NE R AL D E S C R IP T IO N
T he AD7453/43 use advanced design techniques to achieve
very low power dissipation at high throughput rates.
T he AD7453/AD7443 are respectively 12- and 10-bit, low
power, successive-approximation (SAR) analog-to-digital
converters that feature a pseudo differential analog input.
T hese parts operate from a single 2.7 V to 5.25 V power
supply and feature throughput rates up to 600kSPS.
P R O D U C T H IG H LIG H T S
1.Operation with 2.7 V to 5.25 V power supplies.
2.Low Power Consumption.
With a 3V supply, the AD7453/43 offer 3.75mW typ
power consumption for 600kSPS throughput.
3.Pseudo Differential Analog Input.
T he VIN- input can be used as an offset from ground
4.Flexible Power/Serial C lock Speed M anagement.
T he conversion rate is determined by the serial clock,
allowing the power to be reduced as the conversion time
is reduced through the serial clock speed increase. T hese
parts also feature a shutdown mode to maximize power
efficiency at lower throughput rates.
T he parts contains a low-noise, wide bandwidth, differen-
tial track and hold amplifier (T /H) which can handle
input frequencies in excess of 1MHz with the -3dB point
being 20MHz typically. T he reference voltage is 2.5 V
and is applied externally to the VREF pin.
T he conversion process and data acquisition are controlled
using CS and the serial clock allowing the device to inter-
face with Microprocessors or DSPs. T he input signals are
sampled on the falling edge of CS and the conversion is
also initiated at this point.
5.N o Pipeline D elay.
6.Accurate control of the sampling instant via a CS input
and once off conversion control.
T he SAR architecture of these parts ensures that there are
no pipeline delays.
MICROWIRE is a trademark of National Semiconductor Corporation.
SPI and QSPI are trademarks of Motorola, Inc.
REV. PrA 24/05/02
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