Datasheet > AD74111YRU-REEL7

AD74111YRU-REEL7

更新时间： 2024-02-15 21:57:14

品牌	Logo	应用领域
罗彻斯特 - ROCHESTER		光电二极管商用集成电路
页数	文件大小	规格书
21页	995K
描述
SPECIALTY CONSUMER CIRCUIT, PDSO16, TSSOP-16

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AD74111YRU-REEL7 技术参数

是否Rohs认证：	不符合	生命周期：	Obsolete
零件包装代码：	TSSOP	包装说明：	TSSOP-16
针数：	16	Reach Compliance Code：	not_compliant
ECCN代码：	EAR99	HTS代码：	8542.39.00.01
风险等级：	5.27	商用集成电路类型：	CONSUMER CIRCUIT
JESD-30 代码：	R-PDSO-G16	JESD-609代码：	e0
长度：	5 mm	湿度敏感等级：	1
功能数量：	1	端子数量：	16
最高工作温度：	105 °C	最低工作温度：	-40 °C
封装主体材料：	PLASTIC/EPOXY	封装代码：	TSSOP
封装等效代码：	TSSOP16,.25	封装形状：	RECTANGULAR
封装形式：	SMALL OUTLINE, THIN PROFILE, SHRINK PITCH	峰值回流温度（摄氏度）：	240
电源：	2.5,3 V	认证状态：	Not Qualified
座面最大高度：	1.1 mm	子类别：	Other Consumer ICs
最大供电电压 (Vsup)：	2.625 V	最小供电电压 (Vsup)：	2.375 V
表面贴装：	YES	温度等级：	INDUSTRIAL
端子面层：	Tin/Lead (Sn85Pb15)	端子形式：	GULL WING
端子节距：	0.65 mm	端子位置：	DUAL
处于峰值回流温度下的最长时间：	30	宽度：	4.4 mm

AD74111YRU-REEL7 数据手册

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AD74111

4 ꢂ f_S

2 ^ꢂf_S

f_S

ADC

MODULATOR

64 ^ꢂf_S

8 ^ꢂf_S

5th ORDER

COMB FILTER

COMB

COMPENSATION

ADC

RESULT

HALF-BAND

LOW GROUP

DELAY OUTPUT

Figure 5a. ADC Filter Section

DAC

MODULATOR

128 ^ꢂf_S

4 ꢂ f_S

2 ^ꢂf_S

f_S

8 ^ꢂf_S

ZERO ORDER HOLD

SINC COMPENSATION

FILTER

DAC

INPUT

16 ꢂ ZERO

ORDER HOLD

HALF-BAND–

FILTER

HALF-BAND

FILTER

LOW GROUP

DELAY INPUT

Figure 5b. DAC Filter Section

ADC, CAPP, and CAPN Pins

Output Signal Swing

The ADC channel requires two external capacitors to act as

charge reservoirs for the switched capacitor inputs of the sigma-

delta modulator. These capacitors isolate the outputs of the PGA

stage from glitches generated by the sigma-delta modulator. The

capacitor also forms a low-pass filter with the output impedance

of the PGA (approximately 124 Ω), which helps to isolate noise

from the modulator engine. The capacitors should be of good

quality, such as NPO or polypropylene film, with values from

100 pF to 1 nF and should be connected to AGND.

The DAC has an output range of 0.5 V rms/1.414 V p-p about

a bias point equal to V_REFCAP(see Figure 7).

REFCAP

VOUT

1.414V p-p

820ꢃ

2n2F

NPO

Figure 7. Typical Output Circuit

Low Group Delay

Peak Readback

The AD74111 can store the highest ADC value to facilitate level

adjustment of the input signal. Programming the Peak Enable

bit in Control Register E with a 1 will enable ADC Peak Level

Reading. The peak value is stored as a 6-bit number from 0 dB

to –63 dB in 1 dB steps. Reading Control Register F will give the

highest ADC value since the bit was set. The ADC peak register

is automatically cleared after reading.

It is possible to bypass much of the digital filtering by enabling

the Low Group Delay function in Control Register C. By reduc-

ing the amount of filtering the AD74111 applies to input and

output samples, the time delay between the sampling interval

and when the sample is available is greatly reduced. This can be

of benefit in applications such as telematics, where minimal

time delays are important. When the Low Group Delay function

is enabled, the sample rate becomes IMCLK/128.

Decimator Section

The digital decimation filter has a pass-band ripple of 0.2 mdB

and a stop-band attenuation of 120 dB. The filter is an FIR type

with a linear phase response. The group delay at 48 kHz is

910 µs. Output sample rates up to 48 kHz are supported.

Reference

The AD74111 features an on-chip reference whose nominal

value is 1.125 V. A 100 nF ceramic and 10 µF tantalum capacitor

applied at the REFCAP pin are necessary to stabilize the reference.

(See Figure 8.)

Input Signal Swing

The ADC input has an input range of 0.5 V rms/1.414 V p-p

about a bias point equal to V_REFCAP. Figure 6 shows a typical

input filter circuit for use with the AD74111.

REFCAP

10ꢄF

0.1ꢄF

ꢅ

51ꢃ

10nF

AGND

VIN

1.414V p-p

47ꢄF

NPO

Figure 8. Reference Decoupling

If required, an external reference can be used as the reference

source of the ADC and DAC sections. This may be desirable in

situations where multiple devices are required to use the same

value of reference or because of a better temperature coefficient

specification. The internal reference can be disabled via Control

pin (see Figure 9). External references should be of a suitable

value such that the voltage swing of the inputs or outputs is not

affected by being too close to the power supply rails and should

be adequately decoupled.

Figure 6. Typical Input Circuit

DAC Section

The AD74111 DAC channel has a single-ended, analog output.

The DAC has independent software controllable Mute and Volume

Control functions. Control Register G controls the attenuation

factor for the DAC. This register is 10 bits wide, giving 1024

steps of attenuation. The AD74111 output channel employs a

multibit sigma-delta conversion technique that provides a high

quality output with system filtering implemented on-chip.

REV. 0

–9–

1...7 8 91011 12 13...21

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