AD7366
Preliminary Technical Data
SERIAL INTERFACE
9 shows how a 12 SCLK read is used to access the conversion
results.
Figure 9 shows the detailed timing diagram for serial inter-
CONꢀST
facing to the AD7366. On the falling edge of
the
AD7366 will simultaneously convert the selected channels.
These conversions are performed using the on-chip oscillator.
CS
, the conversion will be terminated
On the rising edge of
CS
and DOUTA and DOUTB go back into three-state. If
is not
CONꢀST
After the falling edge of
the BUSY signal goes high,
brought high, but is instead held low for a further 12 SCLK
cycles on either DOUTA or DOUTB, the data from the other
ADC follows on the DOUT pin. This is illustrated in Figure 10
where the case for DOUTA is shown. In this case, the DOUT
indicating the conversion has started. It returns low once the
conversion has been completed. The data can now be read from
the DOUT pins.
CS
and SCLK signals are required to transfer data from the
CS
line in use goes back into three-state on the rising edge of
AD7366. The AD7366 has two output pins corresponding to
each ADC. Data can be read from the AD7366 using both
If the falling edge of SCLK coincides with the falling edge of
CS
, then the falling edge of SCLK is not acknowledged by
D
OUTA & DOUTB, alternatively a single output pin of your
choice can be used. The SCLK input signal provides the
CS
the AD7366, and the next falling edge of the SCLK will be
CS
the first registered after the falling edges of the
CS
.
clock source for the serial interface. The
access data from the AD7366. The falling edge of
goes low to
CS
takes
The
low to indicate the end of a conversion. The data bus is bought
CS
pin can be brought low before the BUSY signal goes
the bus out of three-state and clocks out the MSB of the
conversion result. The data stream consists of 12 bits of data
MSB first. The first bit of the conversion result is valid on the
out of three-state by taking the
utilized to ensure that the MSB is valid on the falling edge of
CS
pin low. This feature can be
CS
first SCLK falling edge after the
falling edge. The
BUSY by bring
low a minimum of t4 nanoseconds before the
subsequent 11 bits of data are clocked out on the falling edge
of the SCLK signal. A minimum of 12 Clock pulses must be
provided to AD7366 to access each conversion result. Figure
CS
BUSY signal goes low. The dotted
this.
line in Figure 7 illustrates
CS
t8
12
SCLK
3
4
5
1
2
t7
t9
t6
t5
t4
D
D
A
DB10
DB9
DB8
DB2
OUT
DB1
DB0
3-STATE
3-STATE
B
OUT
DB11
Figure 9. Serial Interface Timing diagram
CS
t8
SCLK
3
4
5
1
2
10
11
12
13
24
t7
t10
t4
t5
t6
DB1
DB0
DB11
B
DB10
B
DB1
B
DB0
B
DB9
DB10
D
A
A
A
A
A
OUT
THREE-
STATE
THREE-
STATE
DB11
A
Figure 10. Reading Data from Both ADC’s on ONE DOUT Line with 28 SCLK’s
Rev. PrG | Page 16 of 17
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