Datasheet > AD7356YRUZ-500RL7

AD7356YRUZ-500RL7

更新时间： 2024-01-26 16:05:53

品牌	Logo	应用领域
亚德诺 - ADI		/
页数	文件大小	规格书
18页	192K
描述
Differential Input, Dual, 5 MSPS, 12-Bit, SAR ADC

阅读下载

中文翻译

获取价格

数据手册
替代型号

如果您发现信息不准确，欢迎纠错

AD7356YRUZ-500RL7 数据手册

浏览型号AD7356YRUZ-500RL7的Datasheet PDF文件第12页

浏览型号AD7356YRUZ-500RL7的Datasheet PDF文件第13页

浏览型号AD7356YRUZ-500RL7的Datasheet PDF文件第14页

浏览型号AD7356YRUZ-500RL7的Datasheet PDF文件第16页

浏览型号AD7356YRUZ-500RL7的Datasheet PDF文件第17页

浏览型号AD7356YRUZ-500RL7的Datasheet PDF文件第18页

Preliminary Technical Data

SERIAL INTERFACE

AD7356

back into three-state on the 32^ndSCLK falling edge or the rising

Figure 19 shows the detailed timing diagram for serial

interfacing to the AD7356. The serial clock provides the

conversion clock and controls the transfer of information from

the AD7356 during conversion.

edge of , which ever occurs first.

A minimum of 14 serial clock cycles are required to perform

the conversion process and to access data from one conversion

on either data line of the AD7356.

going low provides the

The

signal initiates the data transfer and conversion process.

leading zero to be read in by the microcontroller or DSP. The

remaining data is then clocked out by subsequent SCLK falling

edges, beginning with a second leading zero. Thus, the first

falling clock edge on the serial clock has the leading zero

provided and also clocks out the second leading zero. The 12-bit

result then follows with the final bit in the data transfer valid on

the 14^thfalling edge, having being clocked out on the previous

(13^th) falling edge. In applications with a slower SCLK, it may be

possible to read in data on each SCLK rising edge depending on

The falling edge of

puts the track and hold into hold mode at

which point the analog input is sampled and the bus is taken

out of three-state. The conversion is also initiated at this point

and requires a minimum of 14 SCL to complete. Once 13 SCLK

falling edges have elapsed, the track and hold will go back into

track on the next SCLK rising edge, as shown in Figure 19 at

point B. If a 16 bit data transfer is used on the AD7356, then

two trailing zeros will appear after the final LSB. On the rising

edge of , the conversion will be terminated and SDATA_Aand

SDATA_Bwill go back into three-state. If

but is instead held low for a further 14 SCLK cycles on SDATA_A,

the data from the conversion on ADCB will be output on

SDATA_A.

the SCLK frequency. The first rising edge of SCLK after the

is not brought high,

falling edge would have the second leading zero provided, and

the 13^thrising SCLK edge would have DB0 provided.

Likewise, is

is held low for a further 14 SCLK cycles on

SDATA_A, the data from the conversion on ADCA will be output

on SDATA_B. This is illustrated in Figure 20 where the case for

SDATA_Ais shown. In this case, the SDATA line in use will go

t_ACQUISITION

t₉

t_CONVERT

t₂

t₆

SCLK

t₅

t_QUIET

t₈

t₇

t₃

t₄

OUT

DB11

DB10

DB2

DB9

DB8

DB1

DB0

THREE-STATE

THREE-

STATE

2 LEADING ZEROS

Figure 19. Serial Interface Timing Diagram

t₆

t₂

SCLK

t₅

t₁₀

t₃

t₄

t₇

DB11

DB10

DB9

DB11

ZERO

OUT

THREE-

STATE

THREE-

STATE

2 TRAILING ZEROS

2 LEADING ZEROS

2 LEADING

ZEROS

2 TRAILING ZEROS

Figure 20. Reading Data from Both ADCs on One SDATA Line with 32 SCLKs

Rev. PrC | Page 15 of 18

1...12 13 141516 17 18

中文翻译

下载PDF

AD7356YRUZ-500RL7 替代型号

型号	品牌	替代类型	描述	数据表
AD7356YRUZ-RL	ADI	类似代替	Differential Input, Dual, 5 MSPS, 12-Bit, SAR ADC

与AD7356YRUZ-500RL7相关器件

型号	品牌	获取价格	描述	数据表
AD7356YRUZ-RL	ADI	获取价格	Differential Input, Dual, 5 MSPS, 12-Bit, SAR ADC
AD7357	ADI	获取价格	Differential Input,Dual,Simultaneous Sampling, 4.25 MSPS, 14-Bit, SAR ADC
AD7357_08	ADI	获取价格	Differential Input, Dual, Simultaneous Sampling, 4.2 MSPS, 14-Bit, SAR ADC
AD7357_09	ADI	获取价格	Differential Input, Dual, Simultaneous Sampling, 4.2 MSPS, 14-Bit, SAR ADC
AD7357_17	ADI	获取价格	Differential Input, Dual, Simultaneous Sampling
AD7357BCPZ	ADI	获取价格	Differential Input, Dual, Simultaneous Sampling
AD7357BCPZ-RL	ADI	获取价格	Differential Input, Dual, Simultaneous Sampling
AD7357BRUZ	ADI	获取价格	Differential Input,Dual,Simultaneous Sampling, 4.25 MSPS, 14-Bit, SAR ADC
AD7357BRUZ-500RL7	ADI	获取价格	Differential Input,Dual,Simultaneous Sampling, 4.25 MSPS, 14-Bit, SAR ADC
AD7357BRUZ-RL	ADI	获取价格	Differential Input,Dual,Simultaneous Sampling, 4.25 MSPS, 14-Bit, SAR ADC

与AD7356YRUZ-500RL7相关文章

压敏电阻器在直流电路中的过压保护应用探讨
2024-06-07

1
电感耐压值及其与电感大小的关系
2024-06-07

2
CNY17F光耦合器：特性、应用、封装、引脚功能及替换型号解析
2024-06-07

3
DS1307资料解析：特性、引脚说明、替代推荐
2024-06-07

1

产品中心

服务支持

精选活动

关于我们

帮助中心

AD7356YRUZ-500RL7

AD7356YRUZ-500RL7 数据手册

AD7356YRUZ-500RL7 替代型号

与AD7356YRUZ-500RL7相关器件

与AD7356YRUZ-500RL7相关文章

您还可以找

产品中心

服务支持

精选活动

关于我们

帮助中心

AD7356YRUZ-500RL7

AD7356YRUZ-500RL7 数据手册

AD7356YRUZ-500RL7 替代型号

与AD7356YRUZ-500RL7相关器件

与AD7356YRUZ-500RL7相关文章

您还可以找

您在本页遇到什么问题？