Preliminary Technical Data
AD7356
Once a data transfer is complete and SDATAA and SDATAB have
returned to three-state, another conversion can be initiated after
MODES OF OPERATION
The mode of operation of the AD7356 is selected by controlling
CS
the quiet time, tQUIET, has elapsed by bringing
low again
CS
the (logic) state of the
signal during a conversion. There are
(assuming the required acquisition time has been allowed).
three possible modes of operation: normal mode, partial power-
down mode and full power-down mode. After a conversion has
PARTIAL POWER-DOWN MODE
This mode is intended for use in applications where slower
throughput rates are required. Either the ADC is powered down
between each conversion, or a series of conversions may be
performed at a high throughput rate and the ADC is then
powered down for a relatively long duration between these
bursts of several conversions. When the AD7356 is in partial
power-down, all analog circuitry is powered down except for
the on-chip reference and reference buffers.
CS
been initiated, the point at which
which power-down mode, if any, the device enters. Similarly, if
CS
is pulled high determines
already in a power-down mode,
can control whether the
device returns to normal operation or remains in power-down.
These modes of operation are designed to provide flexible
power management options. These options can be chosen to
optimize the power dissipation/throughput rate ratio for the
differing application requirements.
To enter partial power, the conversion process must be
NORMAL MODE
nd
CS
interrupted by bringing
high anywhere after the 2 falling
This mode is intended for applications needing fastest
throughput rates since the user does not have to worry about
any power-up times with the AD7356 remaining fully powered
at all times. Figure 14 shows the general diagram of the
operation of the AD7356 in this mode.
edge of SCLK and before the 10th falling edge of SCLK, as
CS
shown in Figure 15. Once
window of SCLKs, the part enters partial power-down, the
CS
has been brought high in this
conversion that was initiated by the falling edge of
is
terminated, and SDATAA and SDATAB go back into three-state.
nd
CS
CS
If
is brought high before the 2 SCLK falling edge, the part
remains in normal mode and does not power down. This avoids
1
10
14
CS
accidental power-down due to glitches on the
line.
SCLK
D
D
A
B
OUT
OUT
CS
LEADING ZEROS + CONVERSION RESULT
1
2
10
14
Figure 14. Normal Mode Operation
SCLK
CS
The conversion is initiated on the falling edge of , as
D
D
A
B
THREE-STATE
OUT
OUT
described in the Serial Interface section. To ensure that the part
CS
remains fully powered up at all times,
must remain low until
at least 10 SCLK falling edges have elapsed after the falling edge
Figure 15. Entering Partial Power-Down Mode
th
CS CS
of . If
is brought high any time after the 10 SCLK falling
To exit this mode of operation and power up the AD7356 again,
a dummy conversion is performed. On the falling of , the
edge but before the 14th SCLK falling edge, the part remains
powered up, but the conversion is terminated and SDATAA and
SDATAB go back into three-state. 14 serial clock cycles are
required to complete the conversion and access the conversion
result for the AD7356. The SDATA lines do not return to three-
state after 14 SCLK cycles have elapsed, but instead do so when
CS
device begins to power up, and continues to power up as long as
th
CS
is held low until after the falling edge of the 10 SCLK. The
device is fully powered up after approximately TBD μs has
elapsed, and valid data results from the next conversion, as
nd
CS
shown in Figure 16. If
is brought high before the 2 falling
CS
CS
is brought high again. If
is left low for another 2 SCLK
CS
edge of SCLK, the AD7356 again goes into partial power-down.
CS
cycles, two trailing zeros are clocked out after the data. If
is
This avoids accidental power-up due to glitches on the
Although the device may begin to power up on the falling edge
CS CS
line.
left low for a further 14 SCLK cycles, the result for the other
ADC on board is also accessed on the same SDATA line as
shown in Figure 20 (see the Serial Interface section).
of , if powers down again on the rising edge of . If the
CS
AD7356 is already in partial power-down mode and
is
brought high between the 2nd and 10th falling edges of SCLK, the
device enters full power-down mode.
Once 32 SCLK cycles have elapsed, the SDATA line returns to
nd
CS
three-state on the 32 SCLK falling edge. If
is brought high
prior to this, the SDATA line returns to three-state at that point.
CS
high again sometime prior to the next conversion if so desired,
since the bus still returns to three-state upon completion of the
dual result read.
FULL POWER-DOWN MODE
Thus,
may idle low after 32 SCLK cycles until it is brought
This mode is intended for use in applications where throughput
rates slower than those in the partial power-down mode are
required, as power-up from a full power-down takes
substantially longer than that from a partial power-down. This
Rev. PrC | Page 13 of 18
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