Datasheet > AD73560BB-40

AD73560BB-40

更新时间： 2024-02-13 10:08:07

品牌	Logo	应用领域
亚德诺 - ADI		时钟外围集成电路
页数	文件大小	规格书
39页	641K
描述
IC 0-BIT, 16.384 MHz, OTHER DSP, PBGA119, PLASTIC, BGA-119, Digital Signal Processor

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AD73560BB-40 技术参数

是否Rohs认证：	不符合	生命周期：	Obsolete
零件包装代码：	BGA	包装说明：	PLASTIC, BGA-119
针数：	119	Reach Compliance Code：	not_compliant
ECCN代码：	EAR99	HTS代码：	8542.39.00.01
风险等级：	5.92	地址总线宽度：
桶式移位器：	YES	位大小：	16
边界扫描：	NO	最大时钟频率：	16.384 MHz
外部数据总线宽度：		格式：	FIXED POINT
内部总线架构：	MULTIPLE	JESD-30 代码：	R-PBGA-B119
JESD-609代码：	e0	长度：	22 mm
低功率模式：	YES	端子数量：	119
最高工作温度：	85 °C	最低工作温度：	-40 °C
封装主体材料：	PLASTIC/EPOXY	封装代码：	BGA
封装等效代码：	BGA119,7X17,50	封装形状：	RECTANGULAR
封装形式：	GRID ARRAY	峰值回流温度（摄氏度）：	NOT SPECIFIED
电源：	3.3 V	认证状态：	Not Qualified
RAM（字数）：	8192	座面最大高度：	2.27 mm
子类别：	Digital Signal Processors	最大供电电压：	3.3 V
最小供电电压：	2.7 V	标称供电电压：	3 V
表面贴装：	YES	技术：	CMOS
温度等级：	INDUSTRIAL	端子面层：	Tin/Lead (Sn/Pb)
端子形式：	BALL	端子节距：	1.27 mm
端子位置：	BOTTOM	处于峰值回流温度下的最长时间：	NOT SPECIFIED
宽度：	14 mm	uPs/uCs/外围集成电路类型：	DIGITAL SIGNAL PROCESSOR, OTHER
Base Number Matches：	1

AD73560BB-40 数据手册

Preliminary Technical Data

AD73560

SE SIGNAL SYNCHRONIZED

DSP CONTROL

TO SE

TO MCLK

SDIFS

SDI

TFS

1/2

MCLK

74HC74

MCLK

CLK

AFE

DSP

SCLK

SDO

SECTION

DEVICE 1

RESET

ARESET SIGNAL SYNCHRONIZED

SDOFS

RFS

DSP CONTROL

TO MCLK

TO ARESET

1/2

74HC74

FL0

FL1

SDIFS

SDI

MCLK

CLK

Additional

AD73360

SCLK

SDO

AFE

DEVICE 2

Figure 25 SE and RESET Sync Circuit for Cascaded

Operation

RESET

SDOFS

T here may be some restrictions in cascade operation due

to the number of devices configured in the cascade and the

serial clock rate chosen. T he formula below gives an indi-

cation of whether the combination of sample rate, serial

clock and number of devices can be successfully cascaded.

T his assumes a directly coupled frame sync arrangement

as shown in Figure 24 and does not take any interrupt

latency into account.

74HC74

CLK

Figure 26. Connection of an AD73360 Cascaded to the

AD 73560

[(( De vic eCo unt 1) 16 ) 17]

× − × +

≥

f_S

SCLK

When using the indirectly coupled frame sync configura-

tion in cascaded operation it is necessary to be aware of

the restrictions in sending control word data to all devices

in the cascade. T he user should ensure that there is suffi-

cient time for all the control words to be sent between

reading the last ADC sample and the start of the next

sample period.

Inter facing to the AD E ’s Analog Inputs

T he AD73560 features six signal conditioning inputs.

Each signal conditioning block allows the AD73560 to be

used with either a single-ended or differential signal. T he

applied signal can also be inverted internally by the

AD73560 if required. T he analog input signal to the

AD73560 can be dc-coupled, provided that the dc bias

level of the input signal is the same as the internal refer-

ence level (REFOUT ). Figure 27 shows the recom-

mended differential input circuit for the AD73560. T he

circuit of Figure 27 implements first-order low-pass filters

Connection of a cascade of devices to a DSP, as shown in

Figure 26, is no more complicated than connecting a

single device. Instead of connecting the SDO and SDOFS

to the DSP’s Rx port, these are now daisy-chained to the

SDI and SD IFS of the next device in the cascade. T he

SD O and SDOFS of the final device in the cascade are

connected to the DSP’s Rx port to complete the cascade.

SE and RESET on all devices are fed from the signals that

were synchronized with the MCLK using the circuit of

Figure . T he SCLK from only one device need be con-

nected to the DSP’s SCLK input(s) as all devices will be

running at the same SCLK frequency and phase.

CIN

100⍀

VINPx

10k⍀

VIN

CIN

100⍀

VINNx

10k⍀

0.047␮F

TO INPUT BIAS

CIRCUITRY

REFOUT

VOLTAGE

REFERENCE

REFCAP

0.1␮F

Figure 27. Exam ple Circuit for Differential Input

(DCCoupling)

with a 3 dB point at 34 kHz; these are the only filters that

must be implemented external to the AD 73560 to pre-

vent aliasing of the sampled signal. Since the ADC uses a

highly oversampled approach that transfers the bulk of the

antialiasing filtering into the digital domain, the off-chip

antialiasing filter need only be of a low order. It is recom-

mended that for optimum performance the capacitors used

for the antialiasing filter be of high quality dielectric

(N P O ).

REV. PrA

–3 7 –

1...34 35 363738 39

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