AD73322
APPENDIX B
In Step 10, the programming phase is complete and we now
begin actual channel data read and write. The words loaded into
the serial registers of the two channels at the ADC sampling
event now contain valid ADC data and the words written to the
channels from the DSP’s Tx register will now be interpreted as
DAC words. The DSP Tx register contains the DAC word for
Channel 2.
Configuring an AD73322 to Operate in Data Mode1
This section describes the typical sequence of control words
that are required to be sent to an AD73322 to set it up for data
mode operation. In this sequence Registers B, C and A are
programmed before the device enters data mode. This descrip-
tion panel refers to Table XXIII.
At each sampling event, a pair of SDOFS pulses will be ob-
served which will cause a pair of control (programming) words
to be sent to the device from the DSP. It is advisable that each
pair of control words should program a single register in each
Channel. The sequence to be followed is Channel 2 followed by
Channel 1.
In Step 11, the first DAC word has been transmitted into the
cascade and the ADC word from Channel 2 has been read from
the cascade. The DSP Tx register now contains the DAC word
for Channel 1. As the words being sent to the cascade are now
being interpreted as 16-bit DAC words, the addressing scheme
now changes from one where the address was embedded in the
transmitted word, to one where the serial port now counts the
SDIFS pulses. When the number of SDIFS pulses received
equals the value in the channel count field of Control Register
A, the length of the cascade—each channel updates its DAC
register with the present word in its serial register. In Step 11
each channel has received only one SDIFS pulse; Channel 2
received one SDIFS from the SDOFS of Channel 1 when it sent
its ADC word, and Channel 1 received one SDIFS pulse when
it received the DAC word for Channel 2 from the DSP’s Tx regis-
ter. Therefore, each channel raises its SDOFS line to pass on the
current word in its serial register, and each channel now receives
another SDIFS pulse.
In Step 1, we have the first output sample event following de-
vice reset. The SDOFS signal is raised on both channels2 simul-
taneously, which prepares the DSP Rx register to accept the
ADC word from Channel 2, while SDOFS from Channel 1
becomes an SDIFS to Channel 2. As the SDOFS of Channel 2
is coupled to the DSP’s TFS and RFS, and to the SDIFS of
Channel 1, this event also forces a new control word to be out-
put from the DSP Tx register to Channel 13.
In Step 2, we observe the status of the channels following the
transmission of the first control word. The DSP has received
the output word from Channel 2, while Channel 2 has received
the output word from Channel 1. Channel 1 has received the
Control word destined for Channel 2. At this stage, the SDOFS
of both channels are again raised because Channel 2 has received
Channel 1’s output word, and as it is not a valid control word
addressed to Channel 2, it is passed on to the DSP. Likewise,
Channel 1 has received a control word destined for Channel
2—address field is not zero—and it decrements the address field
of the control word and passes it on.
Step 12 shows the completion of an ADC read and DAC write
cycle. Following Step 11, each channel has received two SDIFS
pulses that equal the setting of the channel count field in Con-
trol Register A. The DAC register in each channel is now up-
dated with the contents of the word that accompanied the SDIFS
pulse that satisfied the channel count requirement. The internal
frame sync counter is now reset to zero and will begin counting
for the next DAC update cycle.
Step 3 shows completion of the first series of control word
writes. The DSP has now received both output words and each
channel has received a control word that addresses control
register B and sets the internal MCLK divider ratio to 1, SCLK
rate to DMCLK/2 and sampling rate to DMCLK/256. Note
that both channels are updated simultaneously as both receive
the addressed control word at the same time. This is an impor-
tant factor in cascaded operation as any latency between updat-
ing the SCLK or DMCLK of channels can result in corrupted
operation. This will not happen in the case of an FSLB configu-
ration as shown here, but must be taken into account in a non-
FSLB configuration. One other important observation of this
sequence is that the data words are received and transmitted in
reverse order, i.e., the ADC words are received by the DSP,
Channel 2 first, then Channel 1 and, similarly, the transmit
words from the DSP are sent to Channel 2 first, then to Chan-
nel 1. This ensures that all channels are updated at the same time.
Steps 10–12 are repeated on each sampling event.
NOTES
1Channel 1 and Channel 2 of the description refer to the two AFE sections of
the AD73322 device.
2The AD73322 is configured as two channels in cascade. The internal cascade
connections between Channels 1 and 2 are detailed in Figure 14. The connec-
tions SDI/SDIFS are inputs to Channel 1 while SDO/SDOFS are outputs from
Channel 2.
3This sequence assumes that the DSP SPORT’s Rx and Tx interrupts are
enabled. It is important to ensure that there is no latency (separation) between
control words in a cascade configuration. This is especially the case when
programming Control Registers A and B as they must be updated synchro-
nously in each channel.
Steps 4–6 are similar to Steps 1–3 but, instead, program Control
Register C to power-up the analog sections of the device (ADCs,
DACs and reference).
Steps 7–9 are similar to Steps 1–3 but, instead, program Control
Register A, with a device count field equal to two channels in
cascade and sets the PGM/DATA bit to one to put the channel
in data mode.
–38–
REV. B
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