Datasheet > 电信电路 > 其他电信集成电路> AD73311LARUZ

AD73311LARUZ

更新时间： 2024-02-02 23:49:03

品牌	Logo	应用领域
亚德诺 - ADI		电信集成电路电信电路光电二极管
页数	文件大小	规格书
36页	357K
描述
Low Cost, Low Power CMOS General Purpose Analog Front End

阅读下载

获取价格

技术参数
数据手册

如果您发现信息不准确，欢迎纠错

AD73311LARUZ 技术参数

是否无铅：	含铅	是否Rohs认证：	符合
生命周期：	Obsolete	零件包装代码：	SOIC
包装说明：	SOP, SOP20,.4	针数：	20
Reach Compliance Code：	unknown	ECCN代码：	EAR99
HTS代码：	8542.39.00.01	风险等级：	5.07
JESD-30 代码：	R-PDSO-G20	JESD-609代码：	e3
长度：	12.8 mm	湿度敏感等级：	1
功能数量：	1	端子数量：	20
最高工作温度：	105 °C	最低工作温度：	-40 °C
封装主体材料：	PLASTIC/EPOXY	封装代码：	SOP
封装等效代码：	SOP20,.4	封装形状：	RECTANGULAR
封装形式：	SMALL OUTLINE	峰值回流温度（摄氏度）：	260
电源：	3 V	认证状态：	Not Qualified
座面最大高度：	2.65 mm	子类别：	Modems
最大压摆率：	0.0125 mA	标称供电电压：	3 V
表面贴装：	YES	技术：	CMOS
电信集成电路类型：	TELECOM CIRCUIT	温度等级：	INDUSTRIAL
端子面层：	Matte Tin (Sn)	端子形式：	GULL WING
端子节距：	1.27 mm	端子位置：	DUAL
处于峰值回流温度下的最长时间：	40	宽度：	7.5 mm
Base Number Matches：	1

AD73311LARUZ 数据手册

AD73311L

PIN FUNCTION DESCRIPTIONS

Number

Mnemonic

Function

VOUTP

VOUTN

AVDD1

AGND1

VINP

VINN

REFOUT

REFCAP

Analog Output from the Positive Terminal of the Output Channel.

Analog Output from the Negative Terminal of the Output Channel.

Analog Power Supply Connection for the Output Driver.

Analog Ground Connection for the Output Driver.

Analog Input to the Positive Terminal of the Input Channel.

Analog Input to the Negative Terminal of the Input Channel.

Buffered Reference Output, which has a nominal value of 1.2 V.

A Bypass Capacitor to AGND2 of 0.1 µF is required for the on-chip reference. The capacitor should

be ﬁxed to this pin.

AVDD2

AGND2

DGND

DVDD

RESET

Analog Power Supply Connection.

Analog Ground/Substrate Connection.

Digital Ground/Substrate Connection.

Digital Power Supply Connection.

Active Low Reset Signal. This input resets the entire chip, resetting the control registers and clearing

the digital circuitry.

SCLK

Output Serial Clock whose rate determines the serial transfer rate to/from the codec. It is used to clock

data or control information to and from the serial port (SPORT). The frequency of SCLK is equal to

the frequency of the master clock (MCLK) divided by an integer number—this integer number being

the product of the external master clock rate divider and the serial clock rate divider.

MCLK

SDO

Master Clock Input. MCLK is driven from an external clock signal.

Serial Data Output of the Codec. Both data and control information may be output on this pin and are

clocked on the positive edge of SCLK. SDO is in three-state when no information is being transmitted

and when SE is low.

SDOFS

SDIFS

Framing Signal Output for SDO Serial Transfers. The frame sync is on bit wide and is active one

SCLK period before the ﬁrst bit (MSB) of each output word. SDOFS is referenced to the positive

edge of SCLK. SDOFS is in three-state when SE is low.

Framing Signal Input for SDI Serial Transfers. The frame sync is one bit wide and is valid one

SCLK period before the ﬁrst bit (MSB) of each input word. SDIFS is sampled on the negative edge of

SCLK and ignored when SE is low.

SDI

Serial Data Input of the Codec. Both data and control information may be input on this pin and are

clocked on the negative edge of SCLK. SDI is ignored when SE is low.

SPORT Enable. Asynchronous input enable pin for the SPORT. When SE is set low by the DSP, the

output pins of the SPORT are three-stated and the input pins are ignored. SCLK is also disabled

internally in order to decrease power dissipation. When SE is brought high, the control and data regis-

ters of the SPORT are at their original values (before SE was brought low); however, the timing

counters and other internal registers are at their reset values.

REV. A

–7–

1...4 5 678 9 10...36

下载PDF

与AD73311LARUZ相关器件

型号	品牌	描述	获取价格	数据表
AD73311LARUZ-REEL	ADI	SPECIALTY TELECOM CIRCUIT, PDSO20, TSSOP-20	获取价格
AD73311LARUZ-REEL7	ADI	SPECIALTY TELECOM CIRCUIT, PDSO20, TSSOP-20	获取价格
AD73311LARUZ-RL7	ADI	Low Cost, Low Power CMOS General Purpose Analog Front End	获取价格
AD73311LARZ	ADI	Single-Channel, 3 V Front-End Processor for General Purpose Applications Including Speech	获取价格
AD73311LARZ-REEL	ADI	Single-Channel, 3 V Front-End Processor for General Purpose Applications Including Speech	获取价格
AD73322	ADI	Low Cost, Low Power CMOS General-Purpose Dual Analog Front End	获取价格

与AD73311LARUZ相关文章

STM32H743技术深度剖析与应用案例探索
2024-05-30

15
LM321中文资料解析：引脚功能介绍、技术特点、技术特性分析
2024-05-30

15
74HC14芯片资料介绍：性能特性分析、引脚介绍
2024-05-30

12
LM1875芯片手册：功放参数分析、引脚说明、电路设计要点
2024-05-30

10

产品中心

服务支持

精选活动

关于我们

帮助中心

AD73311LARUZ

AD73311LARUZ 技术参数

AD73311LARUZ 数据手册

与AD73311LARUZ相关器件

与AD73311LARUZ相关文章

您还可以找

产品中心

服务支持

精选活动

关于我们

帮助中心

AD73311LARUZ

AD73311LARUZ 技术参数

AD73311LARUZ 数据手册

与AD73311LARUZ相关器件

与AD73311LARUZ相关文章

您还可以找

您在本页遇到什么问题？