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AD73311LARU-REEL7 PDF预览

AD73311LARU-REEL7

更新时间: 2024-02-28 17:55:59
品牌 Logo 应用领域
亚德诺 - ADI 电信光电二极管电信集成电路
页数 文件大小 规格书
36页 375K
描述
IC SPECIALTY TELECOM CIRCUIT, PDSO20, TSSOP-20, Telecom IC:Other

AD73311LARU-REEL7 技术参数

是否无铅: 含铅是否Rohs认证: 不符合
生命周期:Active零件包装代码:TSSOP
包装说明:TSSOP-20针数:20
Reach Compliance Code:unknown风险等级:5.63
JESD-30 代码:R-PDSO-G20JESD-609代码:e0
长度:6.5 mm湿度敏感等级:1
功能数量:1端子数量:20
最高工作温度:105 °C最低工作温度:-40 °C
封装主体材料:PLASTIC/EPOXY封装代码:TSSOP
封装形状:RECTANGULAR封装形式:SMALL OUTLINE, THIN PROFILE, SHRINK PITCH
峰值回流温度(摄氏度):240认证状态:COMMERCIAL
座面最大高度:1.1 mm标称供电电压:3 V
表面贴装:YES技术:CMOS
电信集成电路类型:TELECOM CIRCUIT温度等级:INDUSTRIAL
端子面层:TIN LEAD端子形式:GULL WING
端子节距:0.65 mm端子位置:DUAL
处于峰值回流温度下的最长时间:30宽度:4.4 mm
Base Number Matches:1

AD73311LARU-REEL7 数据手册

 浏览型号AD73311LARU-REEL7的Datasheet PDF文件第1页浏览型号AD73311LARU-REEL7的Datasheet PDF文件第2页浏览型号AD73311LARU-REEL7的Datasheet PDF文件第3页浏览型号AD73311LARU-REEL7的Datasheet PDF文件第5页浏览型号AD73311LARU-REEL7的Datasheet PDF文件第6页浏览型号AD73311LARU-REEL7的Datasheet PDF文件第7页 
AD73311L  
Table II. Signal Ranges  
Parameter  
Condition  
Signal Range  
VREFCAP  
VREFOUT  
ADC  
1.2 V 10%  
1.2 V 10%  
1.578 V p-p  
1.0954 V p-p  
Maximum Input Range at VIN  
Nominal Reference Level  
Maximum Voltage  
Output Swing  
DAC  
Single-Ended  
Differential  
1.578 V p-p  
3.156 V p-p  
Nominal Voltage  
Output Swing  
Single-Ended  
Differential  
Output Bias Voltage  
1.0954 V p-p  
2.1909 V p-p  
VREFOUT  
TIMING CHARACTERISTICS (AVDD = DVDD = 2.7 V to 3.6 V; AGND = DGND = 0 V; TA = TMlN to TMAX, unless otherwise noted)  
Limit at  
TA = –40؇C to +105؇C  
Parameter  
Unit  
Description  
Clock Signals  
See Figure 1  
MCLK Period  
MCLK Width High  
MCLK Width Low  
t1  
t2  
t3  
61  
24.4  
24.4  
ns min  
ns min  
ns min  
Serial Port  
t4  
t5  
t6  
t7  
t8  
t9  
t10  
t11  
t12  
t13  
See Figures 3 and 4  
SCLK Period  
SCLK Width High  
SCLK Width Low  
SDI/SDIFS Setup Before SCLK Low  
SDI/SDIFS Hold After SCLK Low  
SDOFS Delay from SCLK High  
SDOFS Hold After SCLK High  
SDO Hold After SCLK High  
SDO Delay from SCLK High  
SCLK Delay from MCLK  
t1  
ns min  
ns min  
ns min  
ns min  
ns min  
ns max  
ns min  
ns min  
ns max  
ns max  
0.4 × t1  
0.4 × t1  
20  
0
10  
10  
10  
10  
30  
t1  
100A  
I
OL  
t2  
TO OUTPUT  
PIN  
2.1V  
C
L
15pF  
100A  
I
OH  
t3  
Figure 1. MCLK Timing  
Figure 2. Load Circuit for Timing Specifications  
t1  
t2  
t3  
MCLK  
t13  
t5  
t6  
SCLK  
*
t4  
SCLK IS INDIVIDUALLY PROGRAMMABLE  
IN FREQUENCY (MCLK/4 SHOWN HERE).  
*
Figure 3. SCLK Timing  
–4–  
REV. A  

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