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AD73311LARU-REEL7 PDF预览

AD73311LARU-REEL7

更新时间： 2024-02-01 01:16:14
品牌 Logo 应用领域
亚德诺 - ADI 电信光电二极管电信集成电路
页数 文件大小 规格书
36页 375K
描述
IC SPECIALTY TELECOM CIRCUIT, PDSO20, TSSOP-20, Telecom IC:Other

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AD73311LARU-REEL7 技术参数

是否无铅： 含铅是否Rohs认证： 不符合
生命周期：Active零件包装代码：TSSOP
包装说明：TSSOP-20针数：20
Reach Compliance Code：unknown风险等级：5.63
JESD-30 代码：R-PDSO-G20JESD-609代码：e0
长度：6.5 mm湿度敏感等级：1
功能数量：1端子数量：20
最高工作温度：105 °C最低工作温度：-40 °C
封装主体材料：PLASTIC/EPOXY封装代码：TSSOP
封装形状：RECTANGULAR封装形式：SMALL OUTLINE, THIN PROFILE, SHRINK PITCH
峰值回流温度（摄氏度）：240认证状态：COMMERCIAL
座面最大高度：1.1 mm标称供电电压：3 V
表面贴装：YES技术：CMOS
电信集成电路类型：TELECOM CIRCUIT温度等级：INDUSTRIAL
端子面层：TIN LEAD端子形式：GULL WING
端子节距：0.65 mm端子位置：DUAL
处于峰值回流温度下的最长时间：30宽度：4.4 mm
Base Number Matches：1

AD73311LARU-REEL7 数据手册

 浏览型号AD73311LARU-REEL7的Datasheet PDF文件第30页浏览型号AD73311LARU-REEL7的Datasheet PDF文件第31页浏览型号AD73311LARU-REEL7的Datasheet PDF文件第32页浏览型号AD73311LARU-REEL7的Datasheet PDF文件第33页浏览型号AD73311LARU-REEL7的Datasheet PDF文件第34页浏览型号AD73311LARU-REEL7的Datasheet PDF文件第35页 
AD73311L  
APPENDIX E  
DAC Timing Control Example  
SE  
SCLK  
SDOFS  
SDO  
The AD73311’s DAC is loaded from the DAC register contents  
just before the ADC register contents are loaded to the serial  
register (SDOFS going high). This default DAC load position  
can be advanced in time to occur earlier with respect to the SDOFS  
going high. Figure 39 shows an example of the ADC unload and  
DAC load sequence. At time t1 the SDOFS is raised to indicate  
that a new ADC word is ready. Following the SDOFS pulse,  
16 bits of ADC data are clocked out on SDO in the subsequent  
16 SCLK cycles finishing at time t2 where the DSP’s SPORT  
will have received the 16-bit word. The DSP may process this  
information and generate a DAC word to be sent to the AD73311.  
Time t3 marks the beginning of the sequence of sending the  
DAC word to the AD73311. This sequence ends at time t4  
where the DAC register will be updated from the 16 bits in the  
AD73311’s serial register. However, the DAC will not be updated  
from the DAC register until time t5, which may not be acceptable in  
certain applications. In order to reduce this delay and load the  
DAC at time t6, the DAC advance register can be programmed with  
a suitable setting corresponding to the required time advance (refer  
to Table VIII for details of DAC Timing Control settings).  
ADC  
WORD  
SDIFS  
SDI  
DAC  
WORD  
DAC  
REGISTER  
UPDATE  
DAC LOAD  
FROM DAC  
REGISTER  
t1  
t2  
t3  
t4  
t5  
t6  
Figure 39. DAC Timing Control  
OUTLINE DIMENSIONS  
Dimensions shown in inches and (mm).  
20-Lead Small Outline IC (R-20)  
0.5118 (13.00)  
0.4961 (12.60)  
20  
11  
1
10  
PIN 1  
0.1043 (2.65)  
0.0926 (2.35)  
0.0291 (0.74)  
؋
 45؇  
0.0098 (0.25)  
0.0500 (1.27)  
0.0157 (0.40)  
8؇  
0؇  
0.0500 0.0192 (0.49)  
0.0118 (0.30)  
0.0040 (0.10)  
SEATING  
PLANE  
0.0125 (0.32)  
0.0091 (0.23)  
(1.27)  
BSC  
0.0138 (0.35)  
20-Lead Shrink Small Outline IC (RS-20)  
20-Lead Thin Shrink Small Outline IC (RU-20)  
0.295 (7.50)  
0.271 (6.90)  
0.260 (6.60)  
0.252 (6.40)  
20  
11  
20  
11  
10  
0.177 (4.50)  
0.169 (4.30)  
0.256 (6.50)  
0.246 (6.25)  
1
10  
1
PIN 1  
0.006 (0.15)  
0.002 (0.05)  
0.0433 (1.10)  
MAX  
0.07 (1.78)  
0.066 (1.67)  
0.078 (1.98) PIN 1  
0.068 (1.73)  
8؇  
0؇  
0.0256 (0.65)  
BSC  
0.0118 (0.30)  
0.0075 (0.19)  
0.028 (0.70)  
0.020 (0.50)  
SEATING  
PLANE  
0.0079 (0.20)  
0.0035 (0.090)  
0.037 (0.94)  
0.022 (0.559)  
8؇  
0؇  
0.0256  
(0.65)  
BSC  
0.008 (0.203)  
0.002 (0.050)  
SEATING  
PLANE  
0.009 (0.229)  
0.005 (0.127)  
–36–  
REV. A  
1...33343536

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