Datasheet > AD73311LARU-REEL7

AD73311LARU-REEL7

更新时间： 2024-02-13 04:14:36

品牌	Logo	应用领域
亚德诺 - ADI		电信光电二极管电信集成电路
页数	文件大小	规格书
36页	375K
描述
IC SPECIALTY TELECOM CIRCUIT, PDSO20, TSSOP-20, Telecom IC:Other

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AD73311LARU-REEL7 技术参数

是否无铅：	含铅	是否Rohs认证：	不符合
生命周期：	Active	零件包装代码：	TSSOP
包装说明：	TSSOP-20	针数：	20
Reach Compliance Code：	unknown	风险等级：	5.63
JESD-30 代码：	R-PDSO-G20	JESD-609代码：	e0
长度：	6.5 mm	湿度敏感等级：	1
功能数量：	1	端子数量：	20
最高工作温度：	105 °C	最低工作温度：	-40 °C
封装主体材料：	PLASTIC/EPOXY	封装代码：	TSSOP
封装形状：	RECTANGULAR	封装形式：	SMALL OUTLINE, THIN PROFILE, SHRINK PITCH
峰值回流温度（摄氏度）：	240	认证状态：	COMMERCIAL
座面最大高度：	1.1 mm	标称供电电压：	3 V
表面贴装：	YES	技术：	CMOS
电信集成电路类型：	TELECOM CIRCUIT	温度等级：	INDUSTRIAL
端子面层：	TIN LEAD	端子形式：	GULL WING
端子节距：	0.65 mm	端子位置：	DUAL
处于峰值回流温度下的最长时间：	30	宽度：	4.4 mm
Base Number Matches：	1

AD73311LARU-REEL7 数据手册

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AD73311L

APPENDIX B

Conﬁguring an AD73311L to Operate in Mixed Mode

the Tx register is loaded with the control word setting for Con-

trol Register B which programs DMCLK = MCLK, the sam-

pling rate to DMCLK/256, SCLK = DMCLK/2.

This section describes a typical sequence of control words that

would be sent to an AD73311L to conﬁgure it for operation in

mixed mode. It is not intended to be a deﬁnitive initialization

sequence, but will show users the typical input/output events

that occur in the programming and Operation Phases¹. This

description panel refers to Table XX.

Steps 7–10 are similar to Steps 4–6 except that Control Register

C is programmed to power up all analog sections (ADC, DAC,

Reference = 1.2 V, REFOUT). In Step 10, a DAC word is sent

to the device. As the channels are in mixed mode, the serial port

interrogates the MSB of the 16-bit word sent to determine whether

it contains DAC data or control information.

Steps 1–3 detail the transfer of the control words to Control

tion. In Step 1, we have the ﬁrst output sample event following

device reset. The SDOFS signal is raised which prepares the

DSP Rx register to accept the ADC word from the AD73311L.

The device is conﬁgured as nonFSLB, which means that the

DSP has control over what is transmitted to the device and in

this case we will not transmit to the device until the output word

has been received from the AD73311L.

Steps 7–10 illustrate the implementation of Control Register

update and DAC update in a single sample period. Note that

this combination is not possible in the FSLB conﬁguration².

Steps 11–15 illustrate a Control Register readback cycle. In Step

13, the device has received a Control Word that addresses Con-

trol Register C for readback (Bit 14 of the Control Word = 1).

When the device receives the readback request, the register

contents are loaded to the serial register as shown in Step 14.

SDOFS is raised in the device, which causes the readback word

to be shifted out toward the DSP. In Step 15, the DSP has

received the readback word (note that the address ﬁeld in the

readback word has been decremented to 111b). Steps 16–18

detail an ADC and DAC update cycle using the nonFSLB con-

ﬁguration. In this case no Control Register update is required.

In Step 2 the DSP has now received the ADC word. Typically,

an interrupt will be generated following reception of the output

words by the DSP. The transmit register of the DSP is loaded

with the control word destined for the AD73311L. This gener-

ates a transmit frame-sync (TFS) that is input to the SDIFS

input of the AD73311L to indicate the start of transmission.

In Step 3 the device has received a control word that addresses

Control Register A and programs the channels into Mixed

Mode-MM and PGM/DATA set to one. Following Step 3, the

device has been programmed into mixed-mode although none of

the analog sections have been powered up (controlled by Con-

trol Register C). Steps 4–6 detail update of Control Register B

in mixed-mode. In Steps 4, 5 the ADC sample, which is invalid

as the ADC section is not yet powered up, is transferred to the

DSP’s Rx section. In the subsequent interrupt service routine

NOTES

¹This sequence assumes that the DSP SPORT's Rx and Tx interrupts are enabled.

It is important to ensure there is no latency (separation) between control words

in a cascade conﬁguration. This is especially the case when programming

Control Registers A and B.

²Mixed mode operation with the FSLB conﬁguration is more restricted in that

only a single word can be sent per sample period.

–30–

REV. A

1...27 28 293031 32 33...36

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AD73311LARU-REEL7 替代型号

型号	品牌	替代类型	描述	数据表
AD73311LARUZ-RL7	ADI	功能相似	Low Cost, Low Power CMOS General Purpose Analog Front End

与AD73311LARU-REEL7相关器件

型号	品牌	描述	获取价格	数据表
AD73311LARUZ	ADI	Low Cost, Low Power CMOS General Purpose Analog Front End	获取价格
AD73311LARUZ-REEL	ADI	SPECIALTY TELECOM CIRCUIT, PDSO20, TSSOP-20	获取价格
AD73311LARUZ-REEL7	ADI	SPECIALTY TELECOM CIRCUIT, PDSO20, TSSOP-20	获取价格
AD73311LARUZ-RL7	ADI	Low Cost, Low Power CMOS General Purpose Analog Front End	获取价格
AD73311LARZ	ADI	Single-Channel, 3 V Front-End Processor for General Purpose Applications Including Speech	获取价格
AD73311LARZ-REEL	ADI	Single-Channel, 3 V Front-End Processor for General Purpose Applications Including Speech	获取价格

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AD73311LARU-REEL7

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