AD7292
Data Sheet
TABLE OF CONTENTS
Features .............................................................................................. 1
ADC Sequence Register (Address 0x03)................................. 21
Configuration Register Bank (Address 0x05) .......................... 21
Alert Limits Register Bank (Address 0x06) ............................ 30
Alert Flags Register Bank (Address 0x07) .............................. 31
Minimum and Maximum Register Bank (Address 0x08) .... 32
Offset Register Bank (Address 0x09)....................................... 32
DAC Buffer Enable Register (Address 0x0A)......................... 33
GPIO Register (Address 0x0B)................................................. 33
Conversion Command Register (Address 0x0E)................... 34
Applications....................................................................................... 1
Functional Block Diagram .............................................................. 1
General Description......................................................................... 1
Revision History ............................................................................... 2
Specifications..................................................................................... 3
ADC Specifications ...................................................................... 3
DAC Specifications....................................................................... 4
General Specifications ................................................................. 5
Temperature Sensor Specifications ............................................ 5
Timing Specifications .................................................................. 6
Absolute Maximum Ratings............................................................ 7
Thermal Resistance ...................................................................... 7
ESD Caution.................................................................................. 7
Pin Configuration and Function Descriptions............................. 8
Typical Performance Characteristics ........................................... 10
Theory of Operation ...................................................................... 15
Analog Inputs.............................................................................. 15
ADC Transfer Functions ........................................................... 16
Temperature Sensor ................................................................... 17
DAC Operation........................................................................... 17
Digital I/O Pins........................................................................... 17
Serial Port Interface (SPI).............................................................. 18
Interface Protocol ....................................................................... 18
Register Structure ........................................................................... 20
Register Descriptions ..................................................................... 21
Vendor ID Register (Address 0x00)......................................... 21
ADC Data Register (Address 0x01)......................................... 21
ADC Conversion Result Registers, VIN0 to VIN7
(Address 0x10 to Address 0x17)............................................... 34
TSENSE Conversion Result Register (Address 0x20) ................ 34
DAC Channel Registers (Address 0x30 to Address 0x33).... 34
ADC Conversion Control ............................................................. 35
ADC Conversion Command.................................................... 35
ADC Sequencer .......................................................................... 36
DAC Output Control ..................................................................... 37
LDAC Operation ........................................................................ 37
Simultaneous Update of All DAC Outputs............................. 37
Alerts and Limits ............................................................................ 38
Alert Limit Monitoring Features.............................................. 38
Hardware Alert Pins................................................................... 38
Alert Flag Bits in the Conversion Result Registers................ 38
Alert Flags Register Bank.......................................................... 39
Minimum and Maximum Conversion Results ...................... 39
Outline Dimensions ....................................................................... 40
Ordering Guide .......................................................................... 40
REVISION HISTORY
9/14—Rev. 0 to Rev. A
Changes to VIN ALERT0 Routing and VIN ALERT1 Routing
Subregisters (Address 0x15 and Address 0x16) Section,
Table 25, and Table 26.................................................................... 27
Changes to Figure 40 and Figure 41 ............................................ 35
Changes to Figure 42...................................................................... 36
Changes to Figure 2.......................................................................... 6
Changed t11 from 4 ns max to 4 ns min and Removed
Endnote 4; Table 5 .......................................................................... 21
Changes to Figure 35...................................................................... 18
Changes to Table 15........................................................................ 21
Changes to VIN Filter Subregister (Address 0x13) Section,
Conversion Delay Control Subregister (Address 0x14) Section,
Table 23, and Table 24.................................................................... 26
10/12—Revision 0: Initial Version
Rev. A | Page 2 of 40
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