AD7274BRM

更新时间： 2024-01-01 11:40:09

品牌	Logo	应用领域
亚德诺 - ADI		/
页数	文件大小	规格书
20页	235K
描述
3MSPS,10-/12-Bit ADCs in 8-Lead TSOT

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技术参数
数据手册
替代型号

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AD7274BRM 技术参数

是否无铅：	含铅	是否Rohs认证：	不符合
生命周期：	Obsolete	零件包装代码：	TSSOP
包装说明：	MO-193BA, TSOT-8	针数：	8
Reach Compliance Code：	not_compliant	ECCN代码：	EAR99
HTS代码：	8542.39.00.01	风险等级：	5.38
最大模拟输入电压：	2.5 V	最小模拟输入电压：
最长转换时间：	0.27 µs	转换器类型：	ADC, SUCCESSIVE APPROXIMATION
JESD-30 代码：	R-PDSO-G8	JESD-609代码：	e0
长度：	2.9 mm	最大线性误差 (EL)：	0.0244%
模拟输入通道数量：	1	位数：	12
功能数量：	1	端子数量：	8
最高工作温度：	85 °C	最低工作温度：	-40 °C
输出位码：	BINARY	输出格式：	SERIAL
封装主体材料：	PLASTIC/EPOXY	封装代码：	VSSOP
封装等效代码：	TSSOP8,.1	封装形状：	RECTANGULAR
封装形式：	SMALL OUTLINE, VERY THIN PROFILE, SHRINK PITCH	峰值回流温度（摄氏度）：	220
电源：	2.5/3.3 V	认证状态：	Not Qualified
采样速率：	3 MHz	采样并保持/跟踪并保持：	TRACK
座面最大高度：	1 mm	子类别：	Analog to Digital Converters
标称供电电压：	3 V	表面贴装：	YES
温度等级：	INDUSTRIAL	端子面层：	Tin/Lead (Sn/Pb)
端子形式：	GULL WING	端子节距：	0.65 mm
端子位置：	DUAL	处于峰值回流温度下的最长时间：	30
宽度：	1.6 mm	Base Number Matches：	1

AD7274BRM 数据手册

PRELIMINARYTECHNICALDATA

Preliminary Technical Data

AD7273/AD7274

Power-up Time

This means, assuming one has the facility to monitor the

ADC supply current, if the ADC powers up in the desired

mode of operation and thus a dummy cycle is not required

to change mode, then neither is a dummy cycle required

to place the track and hold into track.

The power-up time of the AD7273/AD7274 is TBD ns,

which means that with any frequency of SCLK up to 52

MHz, one dummy cycle will always be sufficient to allow

the device to power up. Once the dummy cycle is com-

plete, the ADC will be fully powered up and the input

signal will be acquired properly. The quite time t_QUIET

must still be allowed from the point where the bus goes

back into three-state after the dummy conversion, to the

next falling edge of CS. When running at 3 MSPS

throughput rate, the AD7273/AD7274 will power up and

acquire a signal within ꢁ.5 LSB in one dummy cycle,

i.e. TBD ns.

POWER VERSUS THROUGHPUT RATE

By using the Power-Down mode on the AD7273/AD7274

when not converting, the average power consumption of

the ADC decreases at lower throughput rates. Figure 15

shows how as the throughput rate is reduced, the device

remains in its Power-Down state longer and the average

power consumption over time drops accordingly.

When powering up from the Power-Down mode with a

dummy cycle, as in Figure 14, the track and hold which

was in hold mode while the part was powered down,

returns to track mode after the first SCLK edge the part

receives after the falling edge of CS. This is shown as

point A in Figure 14. Although at any SCLK frequency

one dummy cycle is sufficient to power the device up and

acquire V_IN, it does not necessarily mean that a full

dummy cycle of 16 SCLKs must always elapse to power

up the device and acquire V_INfully; TBD ns will be suffi-

cient to power the device up and acquire the input signal.

If, for example, a 25 MHz SCLK frequency was applied

to the ADC, the cycle time would be 64ꢁ ns. In one

dummy cycle, 64ꢁ ns, the part would be powered up and

V_INacquired fully. However after TBD ns with a 25 MHz

SCLK only TBD SCLK cycles would have elapsed. At

this stage, the ADC would be fully powered up and the

signal acquired. So, in this case the CS can be brought

high after the 1ꢁth SCLK falling edge and brought low

again after a time t_QUIETto initiate the conversion.

For example, if the AD7273/AD7274 is operated in a

continuous sampling mode with a throughput rate of

5ꢁꢁKSPS and a SCLK of 52MHz (V_DDꢀ 3V), and the

device is placed in the Power-Down mode between

conversions, then the power consumption is calculated as

follows. The power dissipation during normal operation is

13.5 mW (V_DDꢀ 3V). If the power up time is one dummy

cycle, i.e. 333ns, and the remaining conversion time is

another cycle, i.e. 333ns, then the AD7273/AD7274 can

be said to dissipate 13.5mW for 666ns during each conver-

sion cycle.If the throughput rate is 5ꢁꢁKSPS, the cycle

time is 2µs and the average power dissipated during each

cycle is (666/2ꢁꢁꢁ) x (13.5 mW)ꢀ 4.5mW.

Figure 15 shows the Power vs. Throughput Rate when

using the Power-Down mode between conversions at 3V.

The Power-Down mode is intended for use with

throughput rates of approximately TBD MSPS and under

as at higher sampling rates there is no power saving made

by using the Power-Down mode.

When power supplies are first applied to the AD7273/

AD7274, the ADC may either power up in the Power-

Down mode or in Normal mode. Because of this, it is best

to allow a dummy cycle to elapse to ensure the part is fully

powered up before attempting a valid conversion. Like-

wise, if it is intended to keep the part in the Power-Down

mode while not in use and the user wishes the part to

power up in Power-Down mode, then the dummy cycle

may be used to ensure the device is in Power-Down by

executing a cycle such as that shown in Figure 13. Once

supplies are applied to the AD7273/AD7274, the power

up time is the same as that when powering up from the

Power-Down mode. It takes approximately TBD ns to

power up fully if the part powers up in Normal mode. It is

not necessary to wait TBD ns before executing a dummy

cycle to ensure the desired mode of operation. Instead, the

dummy cycle can occur directly after power is supplied to

the ADC. If the first valid conversion is then performed

directly after the dummy conversion, care must be taken to

ensure that adequate acquisition time has been allowed. As

mentioned earlier, when powering up from the Power-

Down mode, the part will return to track upon the first

SCLK edge applied after the falling edge of CS.

TBD

TITLE

Figure 15. Power vs Throughput

However, when the ADC powers up initially after supplies

are applied, the track and hold will already be in track.

REV. PrB

–18–

1...15 16 171819 20

中文翻译

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AD7274BRM 替代型号

型号	品牌	替代类型	描述	数据表
AD7274BRMZ-REEL	ADI	类似代替	3 MSPS,10-/12-Bit ADCs in 8-Lead TSOT
AD7274BRMZ	ADI	类似代替	3 MSPS,10-/12-Bit ADCs in 8-Lead TSOT

与AD7274BRM相关器件

型号	品牌	获取价格	描述	数据表
AD7274BRMZ	ADI	获取价格	3 MSPS,10-/12-Bit ADCs in 8-Lead TSOT
AD7274BRMZ	ROCHESTER	获取价格	1-CH 12-BIT SUCCESSIVE APPROXIMATION ADC, SERIAL ACCESS, PDSO8, ROHS COMPLIANT, MO-187AA,
AD7274BRMZ2	ADI	获取价格	3 MSPS,10-/12-Bit ADCs in 8-Lead TSOT
AD7274BRMZ-REEL	ROCHESTER	获取价格	1-CH 12-BIT SUCCESSIVE APPROXIMATION ADC, SERIAL ACCESS, PDSO8, ROHS COMPLIANT, MO-187AA,
AD7274BRMZ-REEL	ADI	获取价格	3 MSPS,10-/12-Bit ADCs in 8-Lead TSOT
AD7274BRMZ-REEL2	ADI	获取价格	3 MSPS,10-/12-Bit ADCs in 8-Lead TSOT
AD7274BUJ-500RL7	ADI	获取价格	3 MSPS,10-/12-Bit ADCs in 8-Lead TSOT
AD7274BUJ-500RL7	ROCHESTER	获取价格	1-CH 12-BIT SUCCESSIVE APPROXIMATION ADC, SERIAL ACCESS, PDSO8, MO-193-BA, TSOT-8
AD7274BUJ-REEL	ADI	获取价格	3MSPS,10-/12-Bit ADCs in 8-Lead TSOT
AD7274BUJZ-500RL7	ADI	获取价格	3 MSPS,10-/12-Bit ADCs in 8-Lead TSOT

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