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AD7274BRM PDF预览

AD7274BRM

更新时间: 2024-02-22 15:08:12
品牌 Logo 应用领域
亚德诺 - ADI /
页数 文件大小 规格书
20页 235K
描述
3MSPS,10-/12-Bit ADCs in 8-Lead TSOT

AD7274BRM 技术参数

是否无铅: 含铅是否Rohs认证: 不符合
生命周期:Obsolete零件包装代码:TSSOP
包装说明:MO-193BA, TSOT-8针数:8
Reach Compliance Code:not_compliantECCN代码:EAR99
HTS代码:8542.39.00.01风险等级:5.38
最大模拟输入电压:2.5 V最小模拟输入电压:
最长转换时间:0.27 µs转换器类型:ADC, SUCCESSIVE APPROXIMATION
JESD-30 代码:R-PDSO-G8JESD-609代码:e0
长度:2.9 mm最大线性误差 (EL):0.0244%
模拟输入通道数量:1位数:12
功能数量:1端子数量:8
最高工作温度:85 °C最低工作温度:-40 °C
输出位码:BINARY输出格式:SERIAL
封装主体材料:PLASTIC/EPOXY封装代码:VSSOP
封装等效代码:TSSOP8,.1封装形状:RECTANGULAR
封装形式:SMALL OUTLINE, VERY THIN PROFILE, SHRINK PITCH峰值回流温度(摄氏度):220
电源:2.5/3.3 V认证状态:Not Qualified
采样速率:3 MHz采样并保持/跟踪并保持:TRACK
座面最大高度:1 mm子类别:Analog to Digital Converters
标称供电电压:3 V表面贴装:YES
温度等级:INDUSTRIAL端子面层:Tin/Lead (Sn/Pb)
端子形式:GULL WING端子节距:0.65 mm
端子位置:DUAL处于峰值回流温度下的最长时间:30
宽度:1.6 mmBase Number Matches:1

AD7274BRM 数据手册

 浏览型号AD7274BRM的Datasheet PDF文件第14页浏览型号AD7274BRM的Datasheet PDF文件第15页浏览型号AD7274BRM的Datasheet PDF文件第16页浏览型号AD7274BRM的Datasheet PDF文件第18页浏览型号AD7274BRM的Datasheet PDF文件第19页浏览型号AD7274BRM的Datasheet PDF文件第20页 
PRELIMINARYTECHNICALDATA  
Preliminary Technical Data  
AD7273/AD7274  
Power-Down Mode  
In order to exit this mode of operation and power the  
AD7273/AD7274 up again, a dummy conversion is per-  
formed. On the falling edge of CS the device will begin to  
power up, and will continue to power up as long as CS is  
held low until after the falling edge of the 1ꢁth SCLK.  
The device will be fully powered up once 16 SCLKs have  
elapsed and valid data will result from the next conversion  
as shown in Figure 14. If CS is brought high before the  
1ꢁth falling edge of SCLK, then the AD7273/AD7274  
will go back into Power- Down again. This avoids acci-  
dental power up due to glitches on the CS line or an inad-  
vertent burst of 8 SCLK cycles while CS is low. So,  
although the device may begin to power up on the falling  
edge of CS, it will power down again on the rising edge  
of CS as long as it occurs before the 1ꢁth SCLK falling  
edge.  
This mode is intended for use in applications where  
slower throughput rates are required; either the ADC is  
powered down between each conversion, or a series of  
conversions may be performed at a high throughput rate  
and then the ADC is powered down for a relatively long  
duration between these bursts of several conversions.  
When the AD7273/AD7274 is in Power-Down, all analog  
circuitry is powered down.  
To enter Power-Down, the conversion process must be  
interrupted by bringing CS high anywhere after the second  
falling edge of SCLK and before the 1ꢁth falling edge of  
SCLK as shown in Figure 13. Once CS has been brought  
high in this window of SCLKs, then the part will enter  
Power-Down and the conversion that was intiated by the  
falling edge of CS will be terminated and SDATA will go  
back into three-state. If CS is brought high before the  
second SCLK falling edge, then the part will remain in  
Normal Mode and will not power-down. This will avoid  
accidental power-down due to glitches on the CS line.  
SCLK  
2
16  
1
10  
THREE-STATE  
SDATA  
INVALID DATA  
Figure 13. Entering Power Down Mode  
THE PART IS FULLY  
POWERED UPWITH V  
THE PART BEGINS  
TO POWER UP  
IN  
FULLY ACQUIRED  
A
16  
16  
SCLK  
10  
1
1
SDATA  
INVALID DATA  
VALID DATA  
Figure 14. Exiting Power Down Mode  
REV. PrB  
17–  

AD7274BRM 替代型号

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