AD7228A
O P AMP SECTIO N
SUP P LY CURRENT
Each voltage-mode D/A converter output is buffered by a unity
gain noninverting CMOS amplifier. T his buffer amplifier is
tested with a 2 kΩ and 100 pF load but will typically drive a
2 kΩ and 500 pF load.
T he AD7228A has a maximum IDD specification of 22 mA and
a maximum ISS of 20 mA over the –55°C to +125°C tempera-
ture range. T his maximum current specification is actually de-
termined by the current at –55°C. Figure 6 shows a typical plot
of power supply current versus temperature.
T he AD7228A can be operated single or dual supply. Operating
the part from single or dual supplies has no effect on the positive-
going settling time. However, the negative-going settling time to
voltages near 0 V in single supply will be slightly longer than the
settling time for dual supply operation. Additionally, to ensure
that the output voltage can go to 0 V in single supply, a transis-
tor on the output acts as a passive pull-down as the output volt-
age nears 0 V. As a result, the sink capability of the amplifier is
reduced as the output voltage nears 0 V in single supply. In dual
supply operation, the full sink capability of 400 µA at 25°C is
maintained over the entire output voltage range. T he single sup-
ply output sink capability is shown in Figure 4. T he negative
VSS also gives improved output amplifier performance allowing
an extended input reference voltage range and giving improved
slew rate at the output.
Figure 6. Power Supply Current vs. Tem perature
AP P LYING TH IS AD 7228A
UNIP O LAR O UTP UT O P ERATIO N
T his is the basic mode of operation for each channel of the
AD7228A, with the output voltage having the same positive po-
larity as VREF. Connections for unipolar output operation are
shown in Figure 7. T he AD7228A can be operated from single
or dual supplies as outlined earlier. T he voltage at the reference
input must never be negative with respect to GND. Failure to
observe this precaution may cause parasitic transistor action and
possible device destruction. T he code table for unipolar output
operation is shown in T able II.
Figure 4. Single Supply Sink Current
T he output broadband noise from the amplifier is 300 µV
peak-to-peak. Figure 5 shows a plot of noise spectral density
versus frequency.
Figure 5. Noise Spectral Density vs. Frequency
D IGITAL INP UTS
T he AD7228A digital inputs are compatible with either T T L or
5 V CMOS levels. All logic inputs are static-protected MOS
gates with typical input currents of less than 1 nA. Internal in-
put protection is achieved by on-chip distributed diodes.
Figure 7. Unipolar Output Circuit
–5–
REV. A
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