Datasheet > 转换器 > 模数转换器> AD7193BRUZ-REEL

AD7193BRUZ-REEL

更新时间： 2024-02-16 05:40:38

品牌	Logo	应用领域
亚德诺 - ADI		转换器模数转换器光电二极管
页数	文件大小	规格书
56页	742K
描述
4-Channel, 4.8 kHz, Ultralow Noise, 24-Bit Sigma-Delta ADC with PGA

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技术参数
数据手册

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AD7193BRUZ-REEL 技术参数

是否无铅：	不含铅	是否Rohs认证：	符合
生命周期：	Active	零件包装代码：	TSSOP
包装说明：	ROHS COMPLIANT, MO-153AE, TSSOP-28	针数：	28
Reach Compliance Code：	unknown	风险等级：	5.72
最大模拟输入电压：	5 V	最小模拟输入电压：	-5 V
转换器类型：	ADC, DELTA-SIGMA	JESD-30 代码：	R-PDSO-G28
JESD-609代码：	e3	长度：	9.7 mm
最大线性误差 (EL)：		湿度敏感等级：	NOT APPLICABLE
模拟输入通道数量：	4	位数：	24
功能数量：	1	端子数量：	28
最高工作温度：	105 °C	最低工作温度：	-40 °C
输出位码：	BINARY, OFFSET BINARY	输出格式：	SERIAL
封装主体材料：	PLASTIC/EPOXY	封装代码：	HTSSOP
封装形状：	RECTANGULAR	封装形式：	SMALL OUTLINE, HEAT SINK/SLUG, THIN PROFILE, SHRINK PITCH
峰值回流温度（摄氏度）：	260	采样速率：	0.0048 MHz
座面最大高度：	1.2 mm	标称供电电压：	5 V
表面贴装：	YES	温度等级：	INDUSTRIAL
端子面层：	MATTE TIN	端子形式：	GULL WING
端子节距：	0.65 mm	端子位置：	DUAL
处于峰值回流温度下的最长时间：	40	宽度：	4.4 mm
Base Number Matches：	1

AD7193BRUZ-REEL 数据手册

AD7193

PIN CONFIGURATION AND FUNCTION DESCRIPTIONS

MCLK1

MCLK2

SCLK

DIN

DOUT/RDY

SYNC

DGND

AGND

BPDSW

REFIN1(–)

REFIN1(+)

AIN8

AD7193

TOP VIEW

(Not to Scale)

P1/REFIN2(+)

P0/REFIN2(–)

AINCOM

AIN1

AIN2

AIN7

AIN3

AIN6

AIN4

AIN5

NC = NO CONNECT

Figure 5. Pin Configuration

Table 5. Pin Function Descriptions

Pin No.

Mnemonic

Description

MCLK1

When the master clock for the device is provided externally by a crystal, the crystal is connected between

MCLK1 and MCLK2.

MCLK2

SCLK

Master Clock Signal for the Device. The AD7193 has an internal 4.92 MHz clock. This internal clock can be

made available on the MCLK2 pin. The clock for the AD7193 can also be provided externally in the form of a

crystal or external clock. A crystal can be tied across the MCLK1 and MCLK2 pins. Alternatively, the MCLK2 pin

can be driven with a CMOS-compatible clock and with the MCLK1 pin remaining unconnected.

Serial Clock Input. This serial clock input is for data transfers to and from the ADC. The SCLK has a Schmitt-

triggered input, making the interface suitable for opto-isolated applications. The serial clock can be

continuous with all data transmitted in a continuous train of pulses. Alternatively, it can be a noncontinuous

clock with the information transmitted to or from the ADC in smaller batches of data.

Chip Select Input. This is an active low logic input used to select the ADC. CS can be used to select the ADC in

systems with more than one device on the serial bus or as a frame synchronization signal in communicating

with the device. CS can be hardwired low, allowing the ADC to operate in 3-wire mode with SCLK, DIN, and

DOUT used to interface with the device.

Digital Output Pin. This pin can function as a general-purpose output bit referenced between AV_DDand

AGND.

Digital Output Pin. This pin can function as a general-purpose output bit referenced between AV_DDand

AGND.

Digital Output Pin/Positive Reference Input. This pin functions as a general-purpose output bit referenced

between AV_DDand AGND. When the REFSEL bit in the configuration register = 1, this pin functions as

REFIN2(+). An external reference can be applied between REFIN2(+) and REFIN2(−). REFIN2(+) can lie

anywhere between AV_DDand AGND + 1 V. The nominal reference voltage, (REFIN2(+) − REFIN2(−)), is AV_DD, but

the part functions with a reference from 1 V to AV_DD.

P1/REFIN2(+)

P0/REFIN2(−)

Digital Output Pin/Negative Reference Input. This pin functions as a general-purpose output bit referenced

between AV_DDand AGND. When the REFSEL bit in the configuration register = 1, this pin functions as

REFIN2(−). This reference input can lie anywhere between AGND and AV_DD− 1 V.

No Connect. Tie this pin to AGND.

AINCOM

Analog Input AIN1 to Analog Input AIN8 are referenced to this input when configured for pseudo differential

operation.

AIN1

AIN2

AIN3

AIN4

Analog Input. This pin can be configured as the positive input of a fully differential input pair when used with

AIN2 or as a pseudo differential input when used with AINCOM.

Analog Input. This pin can be configured as the negative input of a fully differential input pair when used

with AIN1 or as a pseudo differential input when used with AINCOM.

Analog Input. This pin can be configured as the positive input of a fully differential input pair when used with

AIN4 or as a pseudo differential input when used with AINCOM.

Analog Input. This pin can be configured as the negative input of a fully differential input pair when used

with AIN3 or as a pseudo differential input when used with AINCOM.

Rev. A | Page 10 of 56

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与AD7193BRUZ-REEL相关器件

型号	品牌	描述	获取价格	数据表
AD7194	ADI	8-Channel, 4.8 kHz, Ultralow Noise, 24-Bit Sigma-Delta ADC with PGA	获取价格
AD7194BCPZ	ADI	8-Channel, 4.8 kHz, Ultralow Noise, 24-Bit Sigma-Delta ADC with PGA	获取价格
AD7194BCPZ-REEL	ADI	8-Channel, 4.8 kHz, Ultralow Noise, 24-Bit Sigma-Delta ADC with PGA	获取价格
AD7194BCPZ-REEL7	ADI	8-Channel, 4.8 kHz, Ultralow Noise, 24-Bit Sigma-Delta ADC with PGA	获取价格
AD7195	ADI	4.8 kHz, Ultralow Noise, 24-Bit Sigma-Delta ADC with PGA and AC Excitation	获取价格
AD7195BCPZ	ADI	4.8 kHz, Ultralow Noise, 24-Bit Sigma-Delta ADC with PGA and AC Excitation	获取价格

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