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AD7193BRUZ-REEL

更新时间： 2024-02-27 05:28:58
品牌 Logo 应用领域
亚德诺 - ADI 转换器模数转换器光电二极管
页数 文件大小 规格书
56页 742K
描述
4-Channel, 4.8 kHz, Ultralow Noise, 24-Bit Sigma-Delta ADC with PGA

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AD7193BRUZ-REEL 技术参数

是否无铅： 不含铅是否Rohs认证： 符合
生命周期：Active零件包装代码：TSSOP
包装说明：ROHS COMPLIANT, MO-153AE, TSSOP-28针数：28
Reach Compliance Code：unknown风险等级：5.72
最大模拟输入电压：5 V最小模拟输入电压：-5 V
转换器类型：ADC, DELTA-SIGMAJESD-30 代码：R-PDSO-G28
JESD-609代码：e3长度：9.7 mm
最大线性误差 (EL)：湿度敏感等级：NOT APPLICABLE
模拟输入通道数量：4位数：24
功能数量：1端子数量：28
最高工作温度：105 °C最低工作温度：-40 °C
输出位码：BINARY, OFFSET BINARY输出格式：SERIAL
封装主体材料：PLASTIC/EPOXY封装代码：HTSSOP
封装形状：RECTANGULAR封装形式：SMALL OUTLINE, HEAT SINK/SLUG, THIN PROFILE, SHRINK PITCH
峰值回流温度（摄氏度）：260采样速率：0.0048 MHz
座面最大高度：1.2 mm标称供电电压：5 V
表面贴装：YES温度等级：INDUSTRIAL
端子面层：MATTE TIN端子形式：GULL WING
端子节距：0.65 mm端子位置：DUAL
处于峰值回流温度下的最长时间：40宽度：4.4 mm
Base Number Matches：1

AD7193BRUZ-REEL 数据手册

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AD7193  
TIMING °HARA°TERISTI°S  
AVDD = 3 V to 5.25 V, DVDD = 2.7 V to 5.25 V, AGND = DGND = 0 V, Input Logic 0 = 0 V, Input Logic 1 = DVDD, unless otherwise noted.  
Table 2.  
Parameter  
Limit at TMIN, TMAX (B Version)  
Unit  
°onditions/°omments1, 2  
READ AND WRITE OPERATIONS  
t3  
t4  
100  
100  
ns min  
ns min  
SCLK high pulse width  
SCLK low pulse width  
READ OPERATION  
t1  
0
ns min  
ns max  
ns max  
ns min  
ns max  
ns max  
ns min  
ns max  
ns min  
ns min  
CS falling edge to DOUT/RDY active time  
DVDD = 4.75 V to 5.25 V  
DVDD = 2.7 V to 3.6 V  
SCLK active edge to data valid delay4  
DVDD = 4.75 V to 5.25 V  
DVDD = 2.7 V to 3.6 V  
60  
80  
0
60  
80  
10  
80  
0
3
t2  
5, 6  
t5  
Bus relinquish time after CS inactive edge  
t6  
t7  
SCLK inactive edge to CS inactive edge  
SCLK inactive edge to DOUT/RDY high  
10  
WRITE OPERATION  
t8  
0
ns min  
ns min  
ns min  
ns min  
CS falling edge to SCLK active edge setup time4  
Data valid to SCLK edge setup time  
Data valid to SCLK edge hold time  
CS rising edge to SCLK edge hold time  
t9  
t10  
t11  
30  
25  
0
1 Sample tested during initial release to ensure compliance. All input signals are specified with tR = tF = 5 ns (10% to 90% of DVDD) and timed from a voltage level of 1.6 V.  
2 See Figure 3 and Figure 4.  
3 These numbers are measured with the load circuit shown in Figure 2 and defined as the time required for the output to cross the VOL or VOH limits.  
4 The SCLK active edge is the falling edge of SCLK.  
5 These numbers are derived from the measured time taken by the data output to change 0.5 V when loaded with the circuit shown in Figure 2. The measured number  
is then extrapolated back to remove the effects of charging or discharging the 50 pF capacitor. This means that the times quoted in the timing characteristics are the  
true bus relinquish times of the part and, as such, are independent of external bus loading capacitances.  
6 RDY  
RDY  
returns high after a read of the data register. In single conversion mode and continuous conversion mode, the same data can be read again, if required, while  
is high, although care should be taken to ensure that subsequent reads do not occur close to the next output update. If the continuous read feature is enabled, the  
digital word can be read only once.  
Circuit and Timing Diagrams  
I
(1.6mA WITH DV = 5V,  
DD  
SINK  
100µA WITH DV  
= 3V)  
DD  
TO  
OUTPUT  
PIN  
1.6V  
50pF  
I
(200µA WITH DV = 5V,  
DD  
SOURCE  
100µA WITH DV  
= 3V)  
DD  
Figure 2. Load Circuit for Timing Characterization  
Rev. A | Page 7 of 56  
 
 
 
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