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AD7190_08 PDF预览

AD7190_08

更新时间: 2022-12-26 19:16:08
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亚德诺 - ADI /
页数 文件大小 规格书
40页 744K
描述
4.8 kHz Ultralow Noise 24-Bit Sigma-Delta ADC with PGA

AD7190_08 数据手册

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AD7190  
Temp (K) = (Conversion – 0x800000)/2815 K  
Temp (°C) = Temp (K) – 273  
SYSTEM SYNCHRONIZATION  
SYNC  
The  
input allows the user to reset the modulator and the  
digital filter without affecting any of the setup conditions on the  
part. This allows the user to start gathering samples of the analog  
input from a known point in time, that is, the rising edge of  
Following the one point calibration, the internal temperature  
sensor has an accuracy of 2 °C, typically.  
BRIDGE POWER-DOWN SWITCH  
SYNC SYNC  
.
needs to be taken low for four master clock cycles  
In bridge applications such as strain gauges and load cells, the  
bridge itself consumes the majority of the current in the system.  
For example, a 350 Ω load cell requires 15 mA of current when  
excited with a 5 V supply. To minimize the current consumption  
of the system, the bridge can be disconnected (when it is not  
being used) using the bridge power-down switch. Figure 18  
shows how the bridge power-down switch is used. The switch  
can withstand 30 mA of continuous current, and it has an on  
resistance of 10 Ω maximum.  
to implement the synchronization function.  
If multiple AD7190 devices are operated from a common master  
clock, they can be synchronized so that their data registers are  
SYNC  
updated simultaneously. A falling edge on the  
the digital filter and the analog modulator and places the AD7190  
SYNC  
pin resets  
into a consistent, known state. While the  
AD7190 is maintained in this state. On the  
pin is low, the  
SYNC  
rising edge,  
the modulator and filter are taken out of this reset state and, on  
the next clock edge, the part starts to gather input samples again.  
In a system using multiple AD7190 devices, a common signal to  
LOGIC OUTPUTS  
The AD7190 has four general-purpose digital outputs, P0, P1,  
P2, and P3. These are enabled using the GP32EN and GP10EN  
bits in the GPOCON register. The pins can be pulled high or  
low using the P0DAT to P3DAT bits in the GPOCON register;  
that is, the value at the pin is determined by the setting of the  
P0DAT to P3DAT bits. The logic levels for these pins are  
determined by AVDD rather than by DVDD. When the GPOCON  
register is read, the bits P0DAT to P3DAT reflect the actual  
value at the pins. This is useful for short-circuit detection.  
SYNC  
their  
pins synchronizes their operation. This is normally  
done after each AD7190 has performed its own calibration or  
has had calibration coefficients loaded into its calibration  
registers. The conversions from the AD7190s are then  
synchronized.  
The part is taken out of reset on the master clock falling edge  
following the  
multiple devices are being synchronized, the  
be taken high on the master clock rising edge to ensure that all  
devices begin sampling on the master clock falling edge. If the  
SYNC  
low to high transition. Therefore, when  
SYNC  
pin should  
These pins can be used to drive external circuitry, for example,  
an external multiplexer. If an external multiplexer is used to  
increase the channel count, the multiplexer logic pins can be  
controlled via the AD7190 general-purpose output pins. The  
general-purpose output pins can be used to select the active  
multiplexer pin. Because the operation of the multiplexer is  
independent of the AD7190, the AD7190 modulator and filter  
SYNC  
pin is not taken high in sufficient time, it is possible to  
have a difference of one master clock cycle between the devices;  
that is, the instant at which conversions are available differs  
from part to part by a maximum of one master clock cycle.  
SYNC  
The  
In this mode, the rising edge of  
RDY  
pin can also be used as a start conversion command.  
SYNC  
starts conversion, and the  
indicates when the conversion is complete.  
SYNC  
should be reset using the  
pin each time that the multi-  
falling edge of  
plexer channel is changed.  
The disadvantage of this scheme is that the settling time of the  
filter has to be allowed for each data register update. This means  
that the rate at which the data register is updated is reduced. For  
example, if the ADC is configured to use the sinc4 filter, zero  
latency is disabled and chop is disabled, the data register update  
takes four times longer.  
ENABLE PARITY  
The AD7190 also has a parity check function on-chip that  
detects 1-bit errors in the serial communications between the  
ADC and the microprocessor. When the ENPAR bit in the  
mode register is set to 1, parity is enabled. The contents of the  
status register must be transmitted along with each 24-bit  
conversion when the parity function is enabled. To append the  
contents of the status register to each conversion read, the  
DAT_STA bit in the mode register should be set to 1. For each  
conversion read, the parity bit in the status register is  
programmed so that the overall number of 1s transmitted in the  
24-bit data-word is even. Therefore, for example, if the 24-bit  
conversion contains eleven 1s (binary format), the parity bit is  
set to 1 so that the total number of 1s in the serial transmission is  
even. If the microprocessor receives an odd number of 1s, it  
knows that the data received has been corrupted.  
TEMPERATURE SENSOR  
Embedded in the AD7190 is a temperature sensor. This is  
selected using the CH2 bit in the configuration register. When  
the CH2 bit is set to 1, the temperature sensor is enabled. When  
the temperature sensor is selected and bipolar mode is selected,  
the device should return a code of 0x800000 when the temper-  
ature is 0 K. A one-point calibration is needed to get the opti-  
mum performance from the sensor. Therefore, a conversion at a  
known temperature should be recorded. Using this point along  
with the 0 K point, the gain error can be calculated. The  
sensitivity is 2815 codes/°C, typically. The equation for the  
temperature sensor is  
Rev. 0 | Page 3± of 40  
 

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