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AD7152

更新时间： 2024-02-14 23:51:25
品牌 Logo 应用领域
亚德诺 - ADI 转换器
页数 文件大小 规格书
24页 474K
描述
12-Bit Capacitance-to-Digital Converter

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AD7152 技术参数

Source Url Status Check Date：2013-05-01 14:56:16.701是否无铅：含铅
是否Rohs认证：符合生命周期：Obsolete
零件包装代码：TSSOP包装说明：TSSOP, TSSOP10,.19,20
针数：10Reach Compliance Code：compliant
ECCN代码：EAR99HTS代码：8542.39.00.01
风险等级：5.56Is Samacsys：N
模拟集成电路 - 其他类型：ANALOG CIRCUITJESD-30 代码：S-PDSO-G10
JESD-609代码：e3长度：3 mm
湿度敏感等级：1功能数量：1
端子数量：10最高工作温度：85 °C
最低工作温度：-40 °C封装主体材料：PLASTIC/EPOXY
封装代码：TSSOP封装等效代码：TSSOP10,.19,20
封装形状：SQUARE封装形式：SMALL OUTLINE, THIN PROFILE, SHRINK PITCH
峰值回流温度（摄氏度）：260电源：3/3.3 V
认证状态：Not Qualified座面最大高度：1.1 mm
子类别：Other Analog ICs最大供电电流 (Isup)：0.12 mA
最大供电电压 (Vsup)：3.6 V最小供电电压 (Vsup)：2.7 V
标称供电电压 (Vsup)：3.3 V表面贴装：YES
温度等级：INDUSTRIAL端子面层：Matte Tin (Sn)
端子形式：GULL WING端子节距：0.5 mm
端子位置：DUAL处于峰值回流温度下的最长时间：NOT SPECIFIED
宽度：3 mmBase Number Matches：1

AD7152 数据手册

 浏览型号AD7152的Datasheet PDF文件第16页浏览型号AD7152的Datasheet PDF文件第17页浏览型号AD7152的Datasheet PDF文件第18页浏览型号AD7152的Datasheet PDF文件第20页浏览型号AD7152的Datasheet PDF文件第21页浏览型号AD7152的Datasheet PDF文件第22页 
AD7152/AD7153  
CAPDAC  
SINGLE-ENDED CAPACITIVE INPUT  
The CDC full-scale input range of the AD7152/AD7153 can  
be set to ±±.25 pꢁ, ±±.5 pꢁ, ± 1 pꢁ, and ±2 pꢁ in differential  
mode or ±.5 pꢁ, 1 pꢁ, 2 pꢁ, and 4 pꢁ in single-ended mode.  
ꢁor simplicity, the following text and figures use the maximum  
full scale of ±2 pꢁ and +4 pꢁ.  
When configured for a single-ended mode (the CAPDIꢁꢁ bit in  
the Channel 1 Setup or Channel 2 Setup registers is set to ±), the  
AD7152/AD7153 CIN(−) pin is disconnected internally. The  
CDC (without using the CAPDACs) can measure positive input  
capacitance in the range of ± pꢁ to 4 pꢁ (see ꢁigure 29).  
The parts can accept a higher capacitance on the input and the  
common-mode or offset capacitance (unchanging component)  
can be balanced by programmable on-chip CAPDACs.  
CAPDAC(+)  
OFF  
0x0000 ... 0xFFF0  
DATA  
CIN(+)  
CIN(–)  
0pF TO 4pF  
CDC  
CAPDIFF = 0  
CAPDAC(+)  
CIN(+)  
CAPDAC(–)  
OFF  
C
DATA  
CDC  
X
CIN(–)  
0pF TO 4pF  
EXC  
CAPDAC(–)  
C
C
Y
X
Figure 29. CDC Single-Ended Input Mode  
EXC  
The CAPDAC can be used for programmable shifting of the  
input range.  
Figure 28. Using a CAPDAC  
ꢁigure 3± shows how to shift the input range up to 9 pꢁ absolute  
value of capacitance connected to the CIN(+) using  
the CAPDAC(+) only.  
The CAPDAC can be understood as a negative capacitance  
connected internally to the CIN pin. There are two independent  
CAPDACs, one connected to the CIN(+) and the second  
connected to the CIN(–).  
CAPDAC(+)  
5pF  
In differential mode, the relationship between the capacitance  
input and output data can be expressed as  
0x0000 ... 0xFFF0  
DATA  
CIN(+)  
CIN(–)  
0pF TO 4pF  
CDC  
CAPDIFF = 0  
DATA ≈ (CX − CAPDAC(+)) − (CY − CAPDAC(−))  
In single-ended mode, the relationship between the capacitance  
input and output data can be expressed as  
CAPDAC(–)  
OFF  
C
X
5pF TO 9pF  
DATA ≈ CX −(CAPDAC(+) + CAPDAC(−))  
EXC  
The CAPDACs have a 5-bit resolution each, monotonic transfer  
function, are well matched to each other, and have a defined  
temperature coefficient. The CAPDAC full range (absolute  
value) is not factory calibrated and can vary up to ±2±ꢀ with  
the manufacturing process (see the Specifications section,  
ꢁigure 18, and ꢁigure 19).  
Figure 30. Using CAPDAC in Single-Ended Mode  
ꢁigure 31 shows how to shift the input range up to 14 pꢁ  
absolute value of capacitance connected to the CIN(+) using  
both CAPDAC(+) and CAPDAC(−).  
The CAPDACs are shared by the two capacitive channels on the  
AD7152. If the CAPDACs need to be set individually, the host  
controller software should reload the CAPDAC values to the  
AD7152 before executing a conversion on a different channel.  
CAPDAC(+)  
5pF  
0x0000 ... 0xFFF0  
DATA  
CIN(+)  
CIN(–)  
0pF TO 4pF  
CDC  
CAPDIFF = 0  
CAPDAC(–)  
5pF  
C
X
10pF TO 14pF  
EXC  
Figure 31. Using CAPDAC in Single-Ended Mode  
Rev. 0 | Page ±9 of 24  
 
 
 
 
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