AD7013ARS

更新时间： 2024-01-16 17:38:04

品牌	Logo	应用领域
亚德诺 - ADI		/
页数	文件大小	规格书
20页	593K
描述
CMOS TIA IS-54 Baseband Receive Port

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技术参数
数据手册

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AD7013ARS 技术参数

是否Rohs认证：	不符合	生命周期：	Obsolete
零件包装代码：	SSOP	包装说明：	SSOP-28
针数：	28	Reach Compliance Code：	not_compliant
ECCN代码：	5A991.G	HTS代码：	8542.39.00.01
风险等级：	5.92	Is Samacsys：	N
JESD-30 代码：	R-PDSO-G28	JESD-609代码：	e0
长度：	10.2 mm	功能数量：	1
端子数量：	28	最高工作温度：	85 °C
最低工作温度：	-40 °C	封装主体材料：	PLASTIC/EPOXY
封装代码：	SSOP	封装等效代码：	SOP28,.3
封装形状：	RECTANGULAR	封装形式：	SMALL OUTLINE, SHRINK PITCH
峰值回流温度（摄氏度）：	NOT SPECIFIED	电源：	5 V
认证状态：	Not Qualified	座面最大高度：	2 mm
子类别：	Other Telecom ICs	标称供电电压：	5 V
表面贴装：	YES	技术：	CMOS
电信集成电路类型：	TELECOM CIRCUIT	温度等级：	INDUSTRIAL
端子面层：	Tin/Lead (Sn/Pb)	端子形式：	GULL WING
端子节距：	0.65 mm	端子位置：	DUAL
处于峰值回流温度下的最长时间：	NOT SPECIFIED	宽度：	5.3 mm
Base Number Matches：	1

AD7013ARS 数据手册

AD7013

Low Sampling Rate (CR10 = 0)

PCB Layout Considerations

The timing diagram for the receive interface is shown in Figure 4.

The output word rate per channel is equal to 48.6 kHz (MCLK/

128) which corresponds to two times the symbol rate. The low

sampling rate operates in a similar manner to that described for the

high sampling rate.

The use of an analog ground plane is recommended, where the

ground plane extends around the analog circuitry. Both AGND and

DGND should be externally tied together and connected to the

analog ground plane.

Good power supply decoupling is very important for best ADC

performance. A 0.1 µF ceramic decoupling capacitor should be

connected between V_AAand the ground plane. The physical place-

ment of the capacitor (surface mount if possible) is important and

should be placed as close to the pin of the device as is physically

possible. This is also applied to the V_DDpin. Poor power supply

decoupling can lead to a degradation in ADC offsets and SNR.

AUXILIARY DACs

One 10-bit auxiliary DAC and two 8-bit auxiliary DACs are

provided for extra control functions such as automatic gain control,

automatic frequency control and power control. Figure 22

illustrates a simplified block diagram of the auxiliary DACs. The

AUX DACs consist of high impedance current sources, designed to

operate at very low currents while maintaining their DC accuracy.

The DACs are designed using a current segmented architecture.

The bit currents corresponding to each digital input are either

routed to the analog output (bit = 1) or to AGND (bit = 0).

The Bypass pin should be decoupled to the ground plane using a

10 nF capacitor. Large capacitor values are not recommended as

this can cause the reference not to reach its final value, on power

up, before ADC autocalibration has commenced.

Each of the auxiliary DACs has independent low power sleep

modes. The command register has three control bits CR17, CR16

and CR15 which control AUX DAC1, AUX DAC2 and AUX

DAC3 respectively. A logic 0 represents low power sleep mode and

a logic 1 represents normal operation.

Capacitive loading of digital outputs should be minimized as much

as possible if power dissipation is a critical factor. The charging

and discharging of external load capacitances can be a significant

contribution to power dissipation, especially when the AD7013 is in

a low power sleep mode as the DxCLK remains active.

The full-scale currents of the auxiliary DACs are controlled by a

single external resistor, R_SET, connected between the FS ADJUST

pin and AGND. The relationship between full-scale current and

AD7013

V_REF

_SETis given as follows:

(1.23V)

8-BIT

AUX DAC2

8-BIT

AUX DAC3

10-BIT

AUX DAC1

10-Bit AUX DAC

FULL–SCALE

ADJUST

CONTROL

AUX DAC_{FULL SCALE}(mA) = 7992 × V_REF(V)/ R_SET(Ω)

8-Bit AUX DACs

AUX DAC_{FULL SCALE}(mA) = 3984 × V_REF(V)/ R_SET(Ω)

By using smaller values of R_SET, thereby increasing AUX DAC full-

scale current, improved INL and DNL performance is possible as

shown in Table V.

Ω18kΩ

Ω4.5kΩ

Ω9kΩ

R_SET

AGND

Table V. AUX DAC1 INL and DNL as a Function of R_SET

Figure 22. AUX DACs

Worst Case

INL (LSBs)

Worst Case

DNL (LSBs)

R_SET

R_FB

+5V

18 kΩ

9 kΩ

4.5 kΩ

–1.45

+1.22

+1.18

+1.83

+1.59

+1.38

AUX DAC1,

AUX DAC2

OR AUX DAC3

≈

1 TO 4 VOLTS

R_LOAD

OP-295

AD7013

Digital Interface

FS ADJUST

Communication with the Command register, auxiliary DACs, ADC

offset registers and ADC vernier is accomplished via the 3-pin serial

interface. Either one of two loading formats may be used to write

to any of the AD7013’s internal registers. The first format consists

of a single 16-bit serial word to write to any internal register (Table

III). The second format consists of five 16-bit serial words, where

only the last 6 bits in each 16-bit word are used to load five 2-bit

data nibbles. The load sequence for this format is given is Table IV.

The second format is only enable when the Register Address 3 is

used as the destination register as shown in Table I.

R_SET

18kΩ

BYPASS

AUX DAC R_LOAD

R_FB

10-BIT

8-BIT

Ω2.4kΩ

Ω11kΩ

Ω5.4kΩ

Ω4.9kΩ

10nF

Figure 23. External Op Amp Circuitry to Extend Output

Voltage Range

–16–

REV. A

1...13 14 151617 18 19 20

中文翻译

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