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AD7013ARS PDF预览

AD7013ARS

更新时间： 2024-01-19 17:43:02
品牌 Logo 应用领域
亚德诺 - ADI /
页数 文件大小 规格书
20页 593K
描述
CMOS TIA IS-54 Baseband Receive Port

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AD7013ARS 技术参数

是否Rohs认证： 不符合生命周期：Obsolete
零件包装代码：SSOP包装说明：SSOP-28
针数：28Reach Compliance Code：not_compliant
ECCN代码：5A991.GHTS代码：8542.39.00.01
风险等级：5.92Is Samacsys：N
JESD-30 代码：R-PDSO-G28JESD-609代码：e0
长度：10.2 mm功能数量：1
端子数量：28最高工作温度：85 °C
最低工作温度：-40 °C封装主体材料：PLASTIC/EPOXY
封装代码：SSOP封装等效代码：SOP28,.3
封装形状：RECTANGULAR封装形式：SMALL OUTLINE, SHRINK PITCH
峰值回流温度（摄氏度）：NOT SPECIFIED电源：5 V
认证状态：Not Qualified座面最大高度：2 mm
子类别：Other Telecom ICs标称供电电压：5 V
表面贴装：YES技术：CMOS
电信集成电路类型：TELECOM CIRCUIT温度等级：INDUSTRIAL
端子面层：Tin/Lead (Sn/Pb)端子形式：GULL WING
端子节距：0.65 mm端子位置：DUAL
处于峰值回流温度下的最长时间：NOT SPECIFIED宽度：5.3 mm
Base Number Matches：1

AD7013ARS 数据手册

 浏览型号AD7013ARS的Datasheet PDF文件第11页浏览型号AD7013ARS的Datasheet PDF文件第12页浏览型号AD7013ARS的Datasheet PDF文件第13页浏览型号AD7013ARS的Datasheet PDF文件第15页浏览型号AD7013ARS的Datasheet PDF文件第16页浏览型号AD7013ARS的Datasheet PDF文件第17页 
AD7013  
Receive Offset Calibration  
Included in the digital filter is a means by which receive signal  
offsets may be calibrated out. Each channel of the digital low-pass  
filter section has an offset register. The offset register can be made  
to contain a value representing the dc offset of the preceding analog  
circuitry. In normal operation, the value stored in the offset register  
is subtracted from the filter output data before the data appears on  
the serial output pin. By so doing, dc offsets in the I and Q  
channels get calibrated out. Autocalibration or user calibration can  
be selected. Autocalibration will remove internal offsets only while  
user calibration allows the user to write to the offset register in  
order to also remove external offsets.  
0
–10  
–20  
–30  
–40  
–50  
–60  
–70  
–80  
–90  
The offset registers have enough resolution to hold the value of any  
dc offset between ±153 mV (1/8th of the input range). The 10-bit  
offset register represents a twos-complement value which is mapped  
to a 15-bit twos-complement word as shown in Figure 19. The  
contents of the offset registers are subtracted from their respective  
ADC samples.  
–100  
0.0  
7.5  
15.0  
22.5  
30.0  
37.5  
45.0  
52.5  
60.0  
FREQUENCY – kHz  
Figure 16. Receive Root Raised Cosine FIR Filter;  
CR11 = 0, MCLK = 6.2208 MHz  
10-BIT  
I OR Q  
D9  
D8  
D0  
0
0
OFFSET  
0
–10  
–20  
–30  
–40  
–50  
–60  
–70  
–80  
–90  
–100  
REGISTER  
15-BIT  
I OR Q  
OFFSET  
WORD  
D14  
D13  
D12  
D11  
D10  
D2  
D1  
D0  
MSB  
LSB  
Figure 19. Position of the 10-Bit Offset Word Within the  
15-Bit ADC Word  
Receive Offset Adjust: Auto-Calibration (CR13 = 0)  
If receive autocalibration has been selected (CR13 = 0), then the  
AD7013 will initiate an autocalibration routine each time the  
receive path is brought out of the low power sleep mode (CR14 =  
0). The AD7013 internally disconnects the differential inputs from  
the input pins and shorts the differential inputs to measure the  
resulting ADC offset. This is then averaged 16 times to reduce  
ADC noise, and the averaged result is then placed in the offset  
register. The input to the ADC is then switched back for normal  
operation, and after allowing for both analog settling and digital  
filter settling, the first IQ sample pair is output (Figure 14).  
Autocalibration will only remove on-chip offsets.  
0.0  
7.5  
15.0  
22.5  
30.0  
37.5  
45.0  
52.5  
60.0  
FREQUENCY – kHz  
Figure 17. Receive Analog Mode FIR Filter; CR11 = 1,  
MCLK = 5.12 MHz  
0
ANALOG MODE  
–10  
FILTER RESPONSE  
DIGITAL MODE  
FILTER RESPONSE  
–20  
–30  
–40  
–50  
–60  
–70  
–80  
–90  
–100  
Receive Offset Adjust: User Calibration (CR13 = 1)  
When user calibration has been selected, the receive offset register  
can be written to, allowing offsets in the IF/RF demodulation  
circuitry to be also calibrated out. However, the user is now  
responsible for calibrating out receive offsets belonging to the  
AD7013. When the receive path enters the low power mode  
(CR14 = 0), the offset registers remain valid. After powering up,  
the first IQ sample pair is output once time has elapsed for both the  
analog circuitry to settle and also for the output of the digital filter  
to settle as shown in Figure 15.  
0.0  
15.0  
30.0  
45.0  
FREQUENCY – kHz  
Figure 18. Comparision of the Two Frequency Responses  
Where Digital Mode was Clocked at 6.2208 MHz and  
Analog Mode was Clocked at 5.12 MHz  
–14–  
REV. A  
1...11121314151617...20

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