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AD673JD

更新时间： 2024-01-18 14:35:49
品牌 Logo 应用领域
亚德诺 - ADI 转换器
页数 文件大小 规格书
8页 281K
描述
8-Bit A/D Converter

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AD673JD 技术参数

是否Rohs认证： 不符合生命周期：Obsolete
零件包装代码：QLCC包装说明：LCC-20
针数：20Reach Compliance Code：not_compliant
ECCN代码：EAR99HTS代码：8542.39.00.01
风险等级：5.31最大模拟输入电压：5 V
最小模拟输入电压：-5 V最长转换时间：30 µs
转换器类型：ADC, SUCCESSIVE APPROXIMATIONJESD-30 代码：S-PQCC-J20
JESD-609代码：e0长度：8.9662 mm
最大线性误差 (EL)：0.1953%标称负供电电压：-15 V
模拟输入通道数量：1位数：8
功能数量：1端子数量：20
最高工作温度：70 °C最低工作温度：
输出位码：BINARY, OFFSET BINARY输出格式：PARALLEL, 8 BITS
封装主体材料：PLASTIC/EPOXY封装代码：QCCJ
封装等效代码：LDCC20,.4SQ封装形状：SQUARE
封装形式：CHIP CARRIER峰值回流温度（摄氏度）：NOT SPECIFIED
电源：5,-12/-15 V认证状态：Not Qualified
采样速率：0.05 MHz采样并保持/跟踪并保持：SAMPLE
座面最大高度：4.57 mm子类别：Analog to Digital Converters
标称供电电压：5 V表面贴装：YES
技术：BIPOLAR温度等级：COMMERCIAL
端子面层：Tin/Lead (Sn/Pb)端子形式：J BEND
端子节距：1.27 mm端子位置：QUAD
处于峰值回流温度下的最长时间：NOT SPECIFIED宽度：8.9662 mm
Base Number Matches：1

AD673JD 数据手册

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AD673  
GROUNDING CONSIDERATIONS  
TIMING SPECIFICATIONS  
Parameter  
The AD673 provides separate Analog and Digital Common  
connections. The circuit will operate properly with as much as  
±200 mV of common-mode voltage between the two commons.  
This permits more flexible control of system common bussing  
and digital and analog returns.  
Symbol Min Typ Max Units  
CONVERT Pulse Width  
DR Delay from CONVERT tDSC  
Conversion Time  
Data Access Time  
Data Valid after DE High  
Output Float Delay  
tCS  
500  
—
—
—
ns  
1.5 µs  
30 µs  
150 250 ns  
ns  
100 200 ns  
1
tC  
10 20  
In normal operation, the Analog Common terminal may gener-  
ate transient currents of up to 2 mA during a conversion. In ad-  
dition a static current of about 2 mA will flow into Analog  
Common in the unipolar mode after a conversion is complete.  
The Analog Common current will be modulated by the varia-  
tions in input signal.  
tDD  
tHD  
tHL  
0
50  
—
—
—
MICROPROCESSOR INTERFACE CONSIDERATIONS—  
GENERAL  
The absolute maximum voltage rating between the two com-  
mons is ±1 volt. It is recommended that a parallel pair of  
back-to-back protection diodes be connected between the  
commons if they are not connected locally.  
When an analog-to-digital converter like the AD673 is inter-  
faced to a microprocessor, several details of the interface must  
be considered. First, a signal to start the converter must be gen-  
erated; then an appropriate delay period must be allowed to pass  
before valid conversion data may be read. In most applications,  
the AD673 can interface to a microprocessor system with little  
or no external logic.  
CONTROL AND TIMING OF THE AD673  
The operation of the AD673 is controlled by two inputs: CON-  
VERT and DATA ENABLE.  
The most popular control signal configuration consists of de-  
coding the address assigned to the AD673, then gating this sig-  
nal with the system’s WR signal to generate the CONVERT  
pulse, and gating it with RD to enable the output buffers. The  
use of a memory address and memory WR and RD signals de-  
notes “memory-mapped” I/O interfacing, while the use of a  
separate I/O address space denotes “isolated I/O” interfacing.  
Starting a Conversion  
The conversion cycle is initiated by a positive-going CONVERT  
pulse at least 500 ns wide. The rising edge of this pulse resets  
the internal logic, clears the result of the previous conversion,  
and sets DR high. The falling edge of CONVERT begins the  
conversion cycle. When conversion is completed DR returns  
low. During the conversion cycle, DE should be held high. If  
DE goes low during a conversion, the data output buffers will be  
enabled and intermediate conversion results will be present on  
the data output pins. This may cause bus conflicts if other de-  
vices in a system are trying to use the bus.  
Figure 11 shows a generalized diagram of the control logic for  
an AD673 interfaced to an 8-bit data bus, where an address  
ADC ADDR has been decoded. ADC ADDR starts the con-  
verter when written to (the actual data being written to the con-  
verter does not matter) and contains the high byte data during  
read operations.  
V
IH  
+ V  
2
IL  
tC  
CONVERT  
tCS  
tDSC  
DR  
V
OH  
+ V  
2
OL  
Figure 9. Convert Timing  
Reading the Data  
The three-state data output buffers is enabled by DE. Access  
time of these buffers is typically 150 ns (250 maximum). The  
Data outputs remain valid until 50 ns after the enable signal re-  
turns high, and are completely into the high-impedance state  
100 ns later.  
V
IH  
+ V  
2
IL  
DE  
Figure 11. General AD673 Interface to 8-Bit  
Microprocessor  
tDD  
tHD  
HIGH  
IMPEDANCE  
HIGH  
IMPEDANCE  
V
OH  
DATA  
VALID  
DB0–DB7  
V
OL  
tHL  
Figure 10. Read Timing  
–6–  
REV. A  
1...345678

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