Datasheet > AD673JD

AD673JD

更新时间： 2024-01-06 22:18:57

品牌	Logo	应用领域
亚德诺 - ADI		转换器
页数	文件大小	规格书
8页	281K
描述
8-Bit A/D Converter

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技术参数
数据手册

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AD673JD 技术参数

是否Rohs认证：	不符合	生命周期：	Obsolete
零件包装代码：	QLCC	包装说明：	LCC-20
针数：	20	Reach Compliance Code：	not_compliant
ECCN代码：	EAR99	HTS代码：	8542.39.00.01
风险等级：	5.31	最大模拟输入电压：	5 V
最小模拟输入电压：	-5 V	最长转换时间：	30 µs
转换器类型：	ADC, SUCCESSIVE APPROXIMATION	JESD-30 代码：	S-PQCC-J20
JESD-609代码：	e0	长度：	8.9662 mm
最大线性误差 (EL)：	0.1953%	标称负供电电压：	-15 V
模拟输入通道数量：	1	位数：	8
功能数量：	1	端子数量：	20
最高工作温度：	70 °C	最低工作温度：
输出位码：	BINARY, OFFSET BINARY	输出格式：	PARALLEL, 8 BITS
封装主体材料：	PLASTIC/EPOXY	封装代码：	QCCJ
封装等效代码：	LDCC20,.4SQ	封装形状：	SQUARE
封装形式：	CHIP CARRIER	峰值回流温度（摄氏度）：	NOT SPECIFIED
电源：	5,-12/-15 V	认证状态：	Not Qualified
采样速率：	0.05 MHz	采样并保持/跟踪并保持：	SAMPLE
座面最大高度：	4.57 mm	子类别：	Analog to Digital Converters
标称供电电压：	5 V	表面贴装：	YES
技术：	BIPOLAR	温度等级：	COMMERCIAL
端子面层：	Tin/Lead (Sn/Pb)	端子形式：	J BEND
端子节距：	1.27 mm	端子位置：	QUAD
处于峰值回流温度下的最长时间：	NOT SPECIFIED	宽度：	8.9662 mm
Base Number Matches：	1

AD673JD 数据手册

AD673

Full-Scale Calibration

Figure 4a shows how the converter zero may be offset to correct

for initial offset and/or input signal offsets. As shown, the circuit

gives approximately symmetrical adjustment in unipolar mode.

The 5 kΩ thin-film input resistor is laser trimmed to produce a

current which matches the full-scale current of the internal

DAC-plus about 0.3%—when an analog input voltage of 9.961

volts (10 volts – 1 LSB) is applied at the input. The input resis-

tor is trimmed in this way so that if a fine trimming potentio-

meter is inserted in series with the input signal, the input

current at the full scale input voltage can be trimmed down to

match the DAC full-scale current as precisely as desired. How-

ever, for many applications the nominal 9.961 volt full scale can

be achieved to sufficient accuracy by simply inserting a 15 Ω re-

sistor in series with the analog input to Pin 14. Typical full-scale

calibration error will then be within ±2 LSB or ±0.8%. If

more precise calibration is desired, a 200 Ω trimmer should be

used instead. Set the analog input at 9.961 volts, and set the

trimmer so that the output code is just at the transition between

111111 10 and 11111111. Each LSB will then have a weight of

39.06 mV. If a nominal full scale of 10.24 volts is desired

(which makes the LSB have a weight of exactly 40.0 mV), a

100 Ω resistor and a 100 Ω trimmer (or a 200 Ω trimmer with

good resolution) should be used. Of course, larger full-scale

ranges can be arranged by using a larger input resistor, but lin-

earity and full-scale temperature coefficient may be compro-

mised if the external resistor becomes a sizeable percentage of

5 kΩ Figure 3 illustrates the connections required for full-scale

calibration.

Figure 5 shows the nominal transfer curve near zero for an

AD673 in unipolar mode. The code transitions are at the edges

of the nominal bit weights. In some applications it will be prefer-

able to offset the code transitions so that they fall between the

nominal bit weights, as shown in the offset characteristics.

Figure 5. AD673 Transfer Curve—Unipolar Operation

(Approximate Bit Weights Shown for Illustration,

Nominal Bit Weights % 39.06 mV)

This offset can easily be accomplished as shown in Figure 4b. At

balance (after a conversion) approximately 2 mA flows into the

Analog Common terminal. A 10 Ω resistor in series with this

terminal will result in approximately the desired l/2 bit offset of

the transfer characteristics. The nominal 2 mA Analog Common

current is not closely controlled in manufacture. If high accuracy

is required, a 20 Ω potentiometer (connected as a rheostat) can

be used as R1. Additional negative offset range may be obtained

by using larger values of R1. Of course, if the zero transition

point is changed, the full-scale transition point will also move.

Thus, if an offset of 1/2 LSB is introduced, full scale trimming

as described on the previous page should be done with an analog

input of 9.941 volts.

Figure 3. Standard AD673 Connections

Unipolar Offset Calibration

Since the Unipolar Offset is less than ±1/2 LSB for all versions

of the AD673, most applications will not require trimming. Fig-

ure 4 illustrates two trimming methods which can be used if

greater accuracy is necessary.

NOTE: During a conversion, transient currents from the Analog

Common terminal will disturb the offset voltage. Capacitive

decoupling should not be used around the offset network. These

transients will settle appropriately during a conversion. Capaci-

tive decoupling will “pump up” and fail to settle resulting in

conversion errors. Power supply decoupling, which returns to

analog signal common, should go to the signal input side of the

resistive offset network.

Figure 4b.

Figure 4a.

Figure 4. Unipolar Offset Trimming

–4–

REV. A

1 2 345 6 7 8

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