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AD673JD

更新时间： 2024-01-16 06:48:15

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AD673JD 技术参数

是否Rohs认证：	不符合	生命周期：	Obsolete
零件包装代码：	QLCC	包装说明：	LCC-20
针数：	20	Reach Compliance Code：	not_compliant
ECCN代码：	EAR99	HTS代码：	8542.39.00.01
风险等级：	5.31	最大模拟输入电压：	5 V
最小模拟输入电压：	-5 V	最长转换时间：	30 µs
转换器类型：	ADC, SUCCESSIVE APPROXIMATION	JESD-30 代码：	S-PQCC-J20
JESD-609代码：	e0	长度：	8.9662 mm
最大线性误差 (EL)：	0.1953%	标称负供电电压：	-15 V
模拟输入通道数量：	1	位数：	8
功能数量：	1	端子数量：	20
最高工作温度：	70 °C	最低工作温度：
输出位码：	BINARY, OFFSET BINARY	输出格式：	PARALLEL, 8 BITS
封装主体材料：	PLASTIC/EPOXY	封装代码：	QCCJ
封装等效代码：	LDCC20,.4SQ	封装形状：	SQUARE
封装形式：	CHIP CARRIER	峰值回流温度（摄氏度）：	NOT SPECIFIED
电源：	5,-12/-15 V	认证状态：	Not Qualified
采样速率：	0.05 MHz	采样并保持/跟踪并保持：	SAMPLE
座面最大高度：	4.57 mm	子类别：	Analog to Digital Converters
标称供电电压：	5 V	表面贴装：	YES
技术：	BIPOLAR	温度等级：	COMMERCIAL
端子面层：	Tin/Lead (Sn/Pb)	端子形式：	J BEND
端子节距：	1.27 mm	端子位置：	QUAD
处于峰值回流温度下的最长时间：	NOT SPECIFIED	宽度：	8.9662 mm
Base Number Matches：	1

AD673

In systems where this read-write interface is used, at least

30 microseconds (the maximum conversion time) must be al-

lowed to pass between starting a conversion and reading the re-

sults. This delay or “time-out” period can be implemented in a

short software routine such as a countdown loop, enough

dummy instructions to consume 30 microseconds, or enough

actual useful instructions to consume the required time. In tightly-

timed systems, the DR line may be read through an external

three-state buffer to determine precisely when a conversion is

complete. Higher-speed systems may choose to use DR to signal

an interrupt to the processor at the end of a conversion.

CONVERT Pulse Generation

The AD673 is tested with a CONVERT pulse width of 500 ns

and will typically operate with a pulse as short as 300 ns. How-

ever, some microprocessors produce active WR pulses which are

shorter than this. Either of the circuits shown in Figure 13 can

be used to generate an adequate CONVERT pulse for the

AD673. In both circuits, the short low-going WR pulse sets the

CONVERT line high through a flip-flop. The rising edge of DR

(which signifies that the internal logic has been reset) resets

the flip-flop and brings CONVERT low, which starts the

conversion.

Note that t_DSCis slightly longer when the result of the previous

conversion contains a Logic 1 on the LSB. This means that the

actual CONVERT pulse generated by the circuits in Figure 13

will vary slightly in width.

Figure 13b. Using 1/2 74LS74

Figure 13a. Using 74LS00

Figure 12. Typical AD673 Timing Diagram

REV. A

–7–

1...4 5 678

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