Datasheet > AD673JD

AD673JD

更新时间： 2024-02-11 23:21:48

品牌	Logo	应用领域
亚德诺 - ADI		转换器
页数	文件大小	规格书
8页	281K
描述
8-Bit A/D Converter

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数据手册

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AD673JD 技术参数

是否Rohs认证：	不符合	生命周期：	Obsolete
零件包装代码：	QLCC	包装说明：	LCC-20
针数：	20	Reach Compliance Code：	not_compliant
ECCN代码：	EAR99	HTS代码：	8542.39.00.01
风险等级：	5.31	最大模拟输入电压：	5 V
最小模拟输入电压：	-5 V	最长转换时间：	30 µs
转换器类型：	ADC, SUCCESSIVE APPROXIMATION	JESD-30 代码：	S-PQCC-J20
JESD-609代码：	e0	长度：	8.9662 mm
最大线性误差 (EL)：	0.1953%	标称负供电电压：	-15 V
模拟输入通道数量：	1	位数：	8
功能数量：	1	端子数量：	20
最高工作温度：	70 °C	最低工作温度：
输出位码：	BINARY, OFFSET BINARY	输出格式：	PARALLEL, 8 BITS
封装主体材料：	PLASTIC/EPOXY	封装代码：	QCCJ
封装等效代码：	LDCC20,.4SQ	封装形状：	SQUARE
封装形式：	CHIP CARRIER	峰值回流温度（摄氏度）：	NOT SPECIFIED
电源：	5,-12/-15 V	认证状态：	Not Qualified
采样速率：	0.05 MHz	采样并保持/跟踪并保持：	SAMPLE
座面最大高度：	4.57 mm	子类别：	Analog to Digital Converters
标称供电电压：	5 V	表面贴装：	YES
技术：	BIPOLAR	温度等级：	COMMERCIAL
端子面层：	Tin/Lead (Sn/Pb)	端子形式：	J BEND
端子节距：	1.27 mm	端子位置：	QUAD
处于峰值回流温度下的最长时间：	NOT SPECIFIED	宽度：	8.9662 mm
Base Number Matches：	1

AD673JD 数据手册

AD673

BIPOLAR CONNECTION

To obtain the bipolar –5 V to +5 V range with an offset binary

output code, the bipolar offset control pin is left open.

SAMPLE-HOLD AMPLIFIER CONNECTION

TO THE AD673

Many situations in high-speed acquisition systems or digitizing

rapidly changing signals require a sample-hold amplifier (SHA)

in front of the A-D converter. The SHA can acquire and hold a

signal faster than the converter can perform a conversion. A

SHA can also be used to accurately define the exact point in

time at which the signal is sampled. For the AD673, a SHA can

also serve as a high input impedance buffer.

A –5.00 volt signal will give a 8-bit code of 00000000; an input

of 0.00 volts results in an output code of 10000000 and +4.961

volts at the input yields the 11111111 code. The nominal trans-

fer curve is shown in Figure 6.

Figure 8 shows the AD673 connected to the AD582 monolithic

SHA for high speed signal acquisition. In this configuration, the

AD582 will acquire a 10 volt signal in less than 10 µs with a

droop rate less than 100 µV/ms.

DR goes high after the conversion is initiated to indicate that re-

set of the SAR is complete. In Figure 8 it is also used to put the

AD582 into the hold mode while the AD673 begins its conver-

sion cycle. (The AD582 settles to final value well in advance of

the first comparator decision inside the AD673).

DR goes low when the conversion is complete placing the

AD582 back in the sample mode. Configured as shown in Fig-

ure 8, the next conversion can be initiated after a 10 µs delay to

allow for signal acquisition by the AD582.

Figure 6. AD673 Transfer Curve—Bipolar Operation

Note that in the bipolar mode, the code transitions are offset

1/4 LSB such that an input voltage of 0 volts –5 mV to +35 mV

yields the code representing zero (10000000). Each output code

is then centered on its nominal input voltage.

Observe carefully the ground, supply, and bypass capacitor con-

nections between the two devices. This will minimize ground

noise and interference during the conversion cycle.

Full-Scale Calibration

Full-Scale Calibration is accomplished in the same manner as in

Unipolar operation except the full-scale input voltage is +4.61

volts.

Negative Full-Scale Calibration

The circuit in Figure 4a can also be used in Bipolar operation to

offset the input voltage (nominally –5 V) which results in the

000000 00 code. R2 should be omitted to obtain a symmetrical

range.

The bipolar offset control input is not directly TTL compatible

but a TTL interface for logic control can be constructed as

shown in Figure 7.

Figure 8. Sample-Hold Interface to the AD673

Figure 7. Bipolar Offset Controlled by Logic Gate

Gate Output = 1 Unipolar 0 V–10 V Input Range

Gate Output = 0 Bipolar ±5 V Input Range

REV. A

–5–

1 2 3 456 7 8

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