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AD671SD-500 PDF预览

AD671SD-500

更新时间： 2024-02-29 16:07:43
品牌 Logo 应用领域
亚德诺 - ADI 转换器信息通信管理
页数 文件大小 规格书
16页 486K
描述
Monolithic 12-Bit 2 MHz A/D Converter

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AD671SD-500 技术参数

是否Rohs认证： 不符合生命周期：Obsolete
零件包装代码：DIP包装说明：0.300 INCH, SKINNY, CERAMIC, DIP-24
针数：24Reach Compliance Code：not_compliant
ECCN代码：3A001.A.2.CHTS代码：8542.39.00.01
风险等级：5.81Is Samacsys：N
最大模拟输入电压：5 V最小模拟输入电压：-5 V
最长转换时间：0.5 µs转换器类型：ADC, FLASH METHOD
JESD-30 代码：R-CDIP-T24JESD-609代码：e0
长度：30.48 mm最大线性误差 (EL)：0.0977%
标称负供电电压：-5 V模拟输入通道数量：1
位数：12功能数量：1
端子数量：24最高工作温度：125 °C
最低工作温度：-55 °C输出位码：BINARY, OFFSET BINARY, 2'S COMPLEMENT BINARY
输出格式：PARALLEL, WORD封装主体材料：CERAMIC, METAL-SEALED COFIRED
封装代码：DIP封装等效代码：DIP24,.3
封装形状：RECTANGULAR封装形式：IN-LINE
峰值回流温度（摄氏度）：NOT SPECIFIED电源：+-5 V
认证状态：Not Qualified采样速率：2 MHz
采样并保持/跟踪并保持：SAMPLE座面最大高度：5.08 mm
子类别：Analog to Digital Converters标称供电电压：5 V
表面贴装：NO技术：BICMOS
温度等级：MILITARY端子面层：Tin/Lead (Sn/Pb)
端子形式：THROUGH-HOLE端子节距：2.54 mm
端子位置：DUAL处于峰值回流温度下的最长时间：NOT SPECIFIED
宽度：7.62 mmBase Number Matches：1

AD671SD-500 数据手册

 浏览型号AD671SD-500的Datasheet PDF文件第6页浏览型号AD671SD-500的Datasheet PDF文件第7页浏览型号AD671SD-500的Datasheet PDF文件第8页浏览型号AD671SD-500的Datasheet PDF文件第10页浏览型号AD671SD-500的Datasheet PDF文件第11页浏览型号AD671SD-500的Datasheet PDF文件第12页 
AD671  
23  
24  
17  
VLOGIC  
VCC  
VEE  
20  
22  
AIN  
BIT1  
1
BIT12 12  
±
U3  
5V  
+
15V  
Capacitor Values  
0.1 µF (Ceramic) and 10 µF (Tantalum).  
(Surface Mount Chip Capacitors Recom-  
mended to Reduce Lead Inductance).  
ACOM  
ENCODE 16  
2
AD586  
U4  
+V  
IN  
18 DCOM  
15  
14  
13  
DAV  
OTR  
MSB  
8
VOUT  
NOISE  
6
19 REF IN  
Capacitor Locations Directly at Positive and Negative  
Supply Pins to Respective Ground Plane.  
REDUCTION  
6.8µF  
C15  
1µF  
C14  
21 BPO/UPO  
GND  
4
AD671  
Analog Ground  
Digital Ground  
Ground Plane or Wide Ground Return  
Connected to the Analog Power Supply.  
Figure 5. AD586 as Reference Input for AD671  
Ground Plane or Wide Ground Return  
Connected to the Digital Power Supply.  
Proper grounding and decoupling should be a primary design  
objective in any high speed, high resolution system. The AD671  
separates analog and digital grounds to optimize the manage-  
ment of analog and digital ground currents in a system. The  
AD671 is designed to minimize the current flowing from  
ACOM (Pin 22) by directing the majority of the current from  
Analog and Digital  
Ground  
Connected Together Once at the AD671.  
The AD671 is factory trimmed to minimize offset, gain and lin-  
earity errors. In some applications the offset and gain errors of  
the AD671 need to be externally adjusted to zero. This is ac-  
complished by trimming the voltage at BPO/UPO (Pin 21) and  
REFIN (Pin 19). In those applications the AD588, a high preci-  
sion pin programmable voltage reference, is an ideal choice. The  
AD588 includes a reference cell and three additional amplifiers  
which can be configured to provide offset and gain trims for the  
AD671. The circuit in Figure 7 is recommended for calibrating  
offset and gain errors of the AD671 when configured in the 0 V  
to +10 V input range.  
V
CC (+5 V–Pin 23) to VEE (–5 V–Pin 24). Minimizing analog  
ground currents hence reduces the potential for large ground  
voltage drops. This can be especially true in systems that do not  
utilize ground planes or wide ground runs. ACOM is also con-  
figured to be code independent, therefore reducing input depen-  
dent analog ground voltage drops and errors. The input current  
supplied by the external reference (REFIN–Pin 19) and the ma-  
jority of the full-scale input signal (AIN–Pin 20) are also di-  
rected to VÉE. Also critical in any high speed digital design are  
the use of proper digital grounding techniques to avoid potential  
CMOS “ground bounce.” Figure 6 is provided to assist in the  
proper layout, grounding and decoupling techniques.  
+
–
+
5V  
5V  
5V  
10µF  
10µF  
10µF  
Table I is a list of grounding and decoupling guidelines that  
should be reviewed before laying out a printed circuit board.  
0.1µF  
0.1µF  
23  
0.1µF  
24  
VEE  
17  
VLOGIC  
VCC  
+
0 TO 10V  
+
–
+
5V  
5V  
5V  
20  
22  
AIN  
12  
BIT1  
+
15V  
R1  
100  
1
BIT12  
10µF  
10µF  
10µF  
39k  
ACOM  
ENCODE 16  
150pF  
18 DCOM  
15  
14  
13  
DAV  
OTR  
MSB  
0.1µF  
23  
0.1µF  
24  
VEE  
0.1µF  
1µF  
6
4
3
7
50  
1
19 REF IN  
17  
VLOGIC  
10µF  
0.1µF  
0.1µF  
14  
VCC  
21 BPO/UPO  
1µF  
10k  
+
AD671  
AD588  
15  
20  
150  
15  
AIN  
12  
BIT1  
10µF  
+
2
–
15  
16  
1
±
BIT12  
V
5V  
IN  
5
9
10  
8
12 11 13  
–
22  
ACOM  
16  
15  
14  
13  
ENCODE  
R2  
5k  
AGP*  
100k  
50  
18 DCOM  
19  
DAV  
OTR  
MSB  
DGP*  
REF IN  
+
5V REF  
Figure 7. Unipolar (0 V to +10 V) Calibration  
The AD671 is intended to have a nominal 1/2 LSB offset so  
that the exact analog input for a given code will be in the middle  
of that code (halfway between the transitions to the codes above  
it and below it). Thus, the first transition ( from 0000 0000 0000  
to 0000 0000 0001) will occur for an input level of +1/2 LSB  
(1.22 mV for 10 V range). If the offset trim resistor R2 is used,  
21  
BPO/UPO  
AD671  
*GROUND PLANE RECOMMENDED  
Figure 6. AD671 Grounding and Decoupling  
REV. B  
–9–  
1...6789101112...16

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