AD671SD-500

更新时间： 2024-01-29 14:03:56

品牌	Logo	应用领域
亚德诺 - ADI		转换器信息通信管理
页数	文件大小	规格书
16页	486K
描述
Monolithic 12-Bit 2 MHz A/D Converter

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技术参数
数据手册

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AD671SD-500 技术参数

是否Rohs认证：	不符合	生命周期：	Obsolete
零件包装代码：	DIP	包装说明：	0.300 INCH, SKINNY, CERAMIC, DIP-24
针数：	24	Reach Compliance Code：	not_compliant
ECCN代码：	3A001.A.2.C	HTS代码：	8542.39.00.01
风险等级：	5.81	Is Samacsys：	N
最大模拟输入电压：	5 V	最小模拟输入电压：	-5 V
最长转换时间：	0.5 µs	转换器类型：	ADC, FLASH METHOD
JESD-30 代码：	R-CDIP-T24	JESD-609代码：	e0
长度：	30.48 mm	最大线性误差 (EL)：	0.0977%
标称负供电电压：	-5 V	模拟输入通道数量：	1
位数：	12	功能数量：	1
端子数量：	24	最高工作温度：	125 °C
最低工作温度：	-55 °C	输出位码：	BINARY, OFFSET BINARY, 2'S COMPLEMENT BINARY
输出格式：	PARALLEL, WORD	封装主体材料：	CERAMIC, METAL-SEALED COFIRED
封装代码：	DIP	封装等效代码：	DIP24,.3
封装形状：	RECTANGULAR	封装形式：	IN-LINE
峰值回流温度（摄氏度）：	NOT SPECIFIED	电源：	+-5 V
认证状态：	Not Qualified	采样速率：	2 MHz
采样并保持/跟踪并保持：	SAMPLE	座面最大高度：	5.08 mm
子类别：	Analog to Digital Converters	标称供电电压：	5 V
表面贴装：	NO	技术：	BICMOS
温度等级：	MILITARY	端子面层：	Tin/Lead (Sn/Pb)
端子形式：	THROUGH-HOLE	端子节距：	2.54 mm
端子位置：	DUAL	处于峰值回流温度下的最长时间：	NOT SPECIFIED
宽度：	7.62 mm	Base Number Matches：	1

AD671SD-500 数据手册

AD671

The last transition (from 1111 1111 1110 to 1111 1111 1111)

should occur for an analog value 1 1/2 LSB below the nominal

full scale (9.9963 volts for 10.000 volts full scale). The gain er-

ror is the deviation of the actual level at the last transition from

the ideal level. The gain error can be adjusted to zero as shown

in Figures 7, 8 and 9.

Integral nonlinearity refers to the deviation of each individual

code from a line drawn from “zero” through “full scale.” The

point used as “zero” occurs 1/2 LSB (1.22 mV for a 10 V span)

before the first code transition (all zeros to only the LSB on).

“Full scale” is defined as a level 1 1/2 LSB beyond the last code

transition (to all ones). The deviation is measured from the low

side transition of each particular code to the true straight line.

The temperature coefficients for unipolar offset, bipolar zero

and gain error specify the maximum change from the initial

(+25°C) value to the value at T_MINor T_MAX

An ideal ADC exhibits code transitions that are exactly 1 LSB

apart. DNL is the deviation from this ideal value. Thus every

code must have a finite width. Guaranteed no missing codes to

10-bit resolution indicates that all 1024 codes represented by

Bits 1–10 must be present over all operating ranges. Guaranteed

no missing codes to 11- or 12-bit resolution indicates that all

2048 and 4096 codes, respectively, must be present over all op-

erating ranges.

The only effect of power supply error on the performance of the

device will be a small change in gain. The specifications show

the maximum full-scale change from the initial value with the

supplies at the various limits.

S/N+D is the ratio of the rms value of the measured input signal

to the rms sum of all other spectral components, including har-

monics but excluding dc. The value for S/N+D is expressed in

decibels.

The first transition should occur at a level 1/2 LSB above analog

common. Unipolar offset is defined as the deviation of the ac-

tual from that point. This offset can be adjusted as discussed

later. The unipolar offset temperature coefficient specifies the

maximum change of the transition point over temperature, with

or without external adjustments.

ENOB is calculated from the expression SNR = 6.02N +

1.8 dB, where N is equal to the effective number of bits.

THD is the ratio of the rms sum of the first six harmonic com-

ponents to the rms value of the measured input signal and is ex-

pressed as a percentage or in decibels.

In the bipolar mode the major carry transition (0111 1111 1111

to 1000 0000 0000) should occur for an analog value 1/2 LSB

below analog common. The bipolar offset error and temperature

coefficient specify the initial deviation and maximum change in

the error over temperature.

The peak spurious or peak harmonic component is the largest

spectral component excluding the input signal and dc. This

value is expressed in decibels relative to the rms value of a full-

scale input signal.

Theory of Operation

The AD671 uses a successive subranging architecture. The ana-

log to digital conversion takes place in four independent steps or

flashes. The analog input signal is subranged to an intermediate

residue voltage for the final 12-bit result by utilizing multiple

flashes with subtraction DACs (see the AD671 functional block

diagram).

(AD671-500) and less than 50 ns after the falling edge of

ENCODE (AD671–750) or after the falling edge of DAV. The

time window prevents digitally coupled noise from being intro-

duced during the final stages of conversion. An internal timing

generator circuit accurately controls all internal timing.

ACOM

The AD671 can be configured to operate with unipolar (0 V to

+5 V, 0 V to +10 V) or bipolar (±5 V) inputs by connecting

AIN (Pin 20), REFIN (Pin 19) and BPO/UPO (Pin 21) as

shown in Figure 2.

BPO/UPO

BPO/UPO 21

AIN

AIN 20

AIN

The AD671 conversion cycle begins by simply providing an ac-

tive HIGH pulse on the ENCODE pin (Pin 16). The rising

edge of the ENCODE pulse starts the conversion. The falling

edge of the ENCODE pulse is specified to operate within a win-

dow of time: less than 30 ns after the rising edge of ENCODE

REF IN

–

5V REF

0 TO 10V

0 TO 5V

5V TO 5V

Figure 2. Input Range Connections

REV. B

–7–

1...4 5 678 9 10...16

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与AD671SD-500相关器件

型号	品牌	描述	获取价格	数据表
AD671SD-500/883B	ROCHESTER	1-CH 12-BIT FLASH METHOD ADC, PARALLEL ACCESS, CDIP24, SIDE BRAZED, CERAMIC, DIP-24	获取价格
AD671SD-750	ADI	Monolithic 12-Bit 2 MHz A/D Converter	获取价格
AD671SD-750/883B	ROCHESTER	1-CH 12-BIT FLASH METHOD ADC, PARALLEL ACCESS, CDIP24, SIDE BRAZED, CERAMIC, DIP-24	获取价格
AD673	ADI	8-Bit A/D Converter	获取价格
AD673*	ETC	8-Bit A/D Converter	获取价格
AD673JD	ADI	8-Bit A/D Converter	获取价格

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