AD671
it should be trimmed as above, although a different offset can be
set for a particular system requirement. This circuit will give ap-
proximately ±50 mV of offset trim range.
Bipolar calibration is similar to unipolar calibration. First, a sig-
nal 1/2 LSB above negative full scale (–4.9988 V) is applied and
R1 is trimmed to give the first transition (0000 0000 0000 to
0000 0000 0001). Then a signal 1 1/2 LSB below positive full
scale (+4.9963) is applied, and R2 is trimmed to give the last
transition (1111 1111 1110 to 1111 1111 1111).
The gain trim is done by applying a signal 1 1/2 LSBs below the
nominal full scale (9.9963 for a 10 V range). Trim R1 to give
the last transition (1111 1111 1110 to 11111111 1111).
Figure 10 shows the AD671 connected to the 74HC574 Octal
D-type edge triggered latches with 3-state outputs. The latch
can drive highly capacitive loads (i.e., bus lines, I/O ports) while
maintaining the data signal integrity. The maximum set-up and
hold times of the 574 type latch must be less than 20 ns (tDD
and tSS minimum). To satisfy the requirements of the 574 type
latch the recommended logic families are HC, S, AS, ALS, F or
BCT. New data from the AD671 is latched on the rising edge of
the DAV (Pin 24) output pulse. Previous data can be latched by
inverting the DAV output with a 7404 type inverter. See Fig-
ures 20, 21 and 22 for PCB layout recommendations.
The connections for the 0 V to +5 V input range calibration is
shown in Figure 8. The AD586, a +5 V precision voltage refer-
ence, is an excellent choice for this mode of operation because
of its performance, stability and optional fine trim. The AD845
(16 MHz, low power, low cost op amp) is used to maintain the
+5 volts under the dynamically changing load conditions of the
reference input.
+15V
0.1µF
23
24
17
VLOGIC
7
2
3
VCC
AIN
VEE
AD845
6
20
0
TO +5V
8
12
1
BIT1
BIT12
1
4
21 BPO/UPO
+15V
1kΩ
74HC574
DATA BUS
390
–15V
0.1µF
BIT1
1D
1Q
22
ACOM
ENCODE 16
BIT2
BIT3
BIT4
BIT5
BIT6
BIT7
BIT8
DAV
2D
3D
4D
5D
6D
2Q
3Q
+15V
0.1µF
+
15V
18 DCOM
19 REFIN
15
14
DAV
OTR
7
AD845
4
2
3
4Q
5Q
6Q
7Q
8Q
2
U6
6
+V
VOUT
IN
6
MSB 13
7D
TRIM
0.1µF
10kΩ
–15V
5
8D
CLK
NOISE
REDUCTION
AD671
8
OC
AD586
1µF
74HC574
GND
4
BIT9
BIT10
BIT11
BIT12
1Q
1D
2D
3D
4D
2Q
3Q
4Q
Figure 8. Unipolar (0 V to +5 V) Calibration
5D
6D
7D
8D
U5
5Q
6Q
7Q
8Q
The AD671 offset error must be trimmed within the analog in-
put path, either directly in front of the AD671 or within the sig-
nal conditioning chain, eliminating offset errors induced by the
signal conditioning circuitry. Figure 8 shows an example of how
the offset error can be trimmed in front of the AD671. The
AD586 is configured in the optional fine trim mode to provide
+6%/–2% (+240 LSBs/–80 LSBs) of gain trim. The procedure
for trimming the offset and gain errors is similar to that used for
the unipolar 10 V range with the analog input values set to one-
half the 10 V range values.
3-STATE
CONTROL
CLK
AD671
OC
Figure 10. AD671 to Output Latches
An Out of Range condition exists when the analog input voltage
is beyond the input range (0 V to +5 V, 0 V to +10 V, ±5 V) of
the converter. OTR (Pin 14) is set low when the analog input
voltage is within the analog input range. OTR is set HIGH and
will remain HIGH when the analog input voltage exceeds the
input range by typically 1/2 LSB (OTR transition is tested to
±6 LSBs of accuracy) from the center of the ± full-scale output
codes. OTR will remain HIGH until the analog input is within
the input range and another conversion is completed. By logical
ANDing OTR with the MSB and its complement overrange
high or underrange low conditions can be detected. Table II is a
truth table for the over/under range circuit in Figure 11. Sys-
tems requiring programmable gain conditioning prior to the
AD671 can immediately detect an out of range condition, thus
eliminating gain selection iterations.
؎
The connections for the bipolar input range is shown in Figure
9. The AD588 is configured to provide dual +5 V outputs. Pro-
viding a +5 V reference voltage for the AD671 gain trim and the
+5 V BPO/UPO input for the bipolar offset trim.
23
24
VEE
17
VLOGIC
VCC
±
5V
20
AIN
12
BIT1
6.2kΩ
+
15V
R1
100
1
BIT12
39k
22
ACOM
ENCODE 16
150pF
18 DCOM
15
14
13
DAV
OTR
MSB
1µF
6
4
3
7
50
1
19 REF IN
10µF
0.1µF
0.1µF
14
21 BPO/UPO
R2
100
150pF
AD671
AD588
15
50
15
10µF
0
0
1
1
0
1
0
1
In Range
In Range
Underrange
Overrange
+
2
–
15
16
5
9
10
8
12 11 13
Figure 9. Bipolar (±5 V) Calibration
–10–
REV. B
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