AD6643BCPZRL7-200

更新时间： 2024-01-04 08:22:33

品牌	Logo	应用领域
亚德诺 - ADI		接收机
页数	文件大小	规格书
36页	1331K
描述
Dual IF Receiver 1.8 V supply voltages Internal ADC voltage reference

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数据手册

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AD6643BCPZRL7-200 数据手册

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AD6643

SWITCHING SPECIFICATIONS

Table 4.

Parameter

Symbol

Temperature Min

Typ

Max

Unit

CLOCK INPUT PARAMETERS

Input Clock Rate

Full

62ꢀ

200

MHz

MSPS

Conversion Rate¹

4.0

CLK Period—Divide-by-1 Mode²

CLK Pulse Width High²

t_CLK

t_CH

Divide-by-1 Mode, DCS Enabled

Divide-by-1 Mode, DCS Disabled

Divide-by-2 Through Divide-by-8 Modes, DCS Enabled

DATA OUTPUT PARAMETERS (DATA, OR)

LVDS Mode

Full

2.2ꢀ

2.37ꢀ 2.ꢀ

0.8

2.ꢀ

2.7ꢀ

2.62ꢀ ns

Data Propagation Delay²

DCO Propagation Delay²

DCO to Data Skew²

t_PD

t_DCO

t_SKEW

Full

4.8

ꢀ.ꢀ

Cycles³

ps rms

ꢁs

0.1

0.7

1.0

0.1

2ꢀ0

1.3

Pipeline Delay (Latency)

NSR Enabled

Aperture Delay⁴

Aperture Uncertainty (Jitter)⁴

Wake-Up Time (from Standby)

Wake-Up Time (from Power-Down)

OUT-OF-RANGE RECOVERY TIME

t_A

t_J

ꢁs

Cycles

¹Conversion rate is the clock rate after the divider.

²See Figure 2 for timing diagram.

³Cycles refers to ADC input sample rate cycles.

⁴Not shown in timing diagrams.

TIMING SPECIFICATIONS

Table 5.

Parameter

Conditions

Min Typ Max Unit

SYNC TIMING REQUIREMENTS

See Figure 3 for timing details

t_SSYNC

t_HSYNC

SYNC to the rising edge of CLK setup time

SYNC to the rising edge of CLK hold time

See Figure 4ꢀ for SPI timing diagram

0.3

0.4

SPI TIMING REQUIREMENTS

t_DS

t_DH

t_CLK

t_S

t_H

t_HIGH

t_LOW

t_{EN_SDIO}

Setup time between the data and the rising edge of SCLK

Hold time between the data and the rising edge of SCLK

Period of the SCLK

Setup time between CSB and SCLK

Hold time between CSB and SCLK

Minimum period that SCLK should be in a logic high state

Minimum period that SCLK should be in a logic low state

Time required for the SDIO pin to switch from an input to an output

relative to the SCLK falling edge (not shown in Figure 4ꢀ)

t_{DIS_SDIO}

Time required for the SDIO pin to switch from an output to an input

relative to the SCLK rising edge (not shown in Figure 4ꢀ)

Rev. 0 | Page 8 of 36

1...5 6 789 10 11...36

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