AD6643BCPZRL7-200

更新时间： 2024-01-12 19:06:53

品牌	Logo	应用领域
亚德诺 - ADI		接收机
页数	文件大小	规格书
36页	1331K
描述
Dual IF Receiver 1.8 V supply voltages Internal ADC voltage reference

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AD6643BCPZRL7-200 数据手册

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AD6643

Parameter¹

Temperature

Min

Typ

Max

Unit

TWO TONE SFDR

2ꢀ°C

Full

dBc

f_IN= 184.12 MHz, 187.12 MHz (−7 dBFS)

CROSSTALK²

9ꢀ

FULL POWER BANDWIDTH³

NOISE BANDWIDTH⁴

2ꢀ°C

400

1000

MHz

¹For a complete set of definitions, see the AN-83ꢀ Application Note, Understanding High Speed ADC Testing and Evaluation.

²Crosstalk is measured at 100 MHz with −1 dBFS on one channel and with no input on the alternate channel.

³Full power bandwidth is the bandwidth of operation where typical ADC performance can be achieved.

⁴Noise bandwidth is the −3 dB bandwidth for the ADC inputs across which noise may enter the ADC and it is not attenuated internally.

DIGITAL SPECIFICATIONS

AVDD = 1.8 V, DRVDD = 1.8 V, maximum sample rate, VIN = −1.0 dBFS differential input, 1.75 V p-p full-scale input range,

DCS enabled, default SPI, unless otherwise noted.

Table 3.

Parameter

Temperature Min

Typ

Max

Unit

DIFFERENTIAL CLOCK INPUTS (CLK+, CLK−)

Logic Compliance

Internal Common-Mode Bias

Differential Input Voltage

Input Voltage Range

Input Common-Mode Range

Input Current Level

High

CMOS/LVDS/LVPECL

Full

0.9

3.6

V p-p

Full

0.3

AGND

0.9

AVDD

1.4

Full

−22

−10

μA

kΩ

Low

Input Capacitance

Input Resistance

SYNC INPUT

Logic Compliance

Internal Bias

Input Voltage Range

Input Voltage Level

High

CMOS/LVDS

0.9

Full

AGND

AVDD

Full

1.2

AGND

AVDD

0.6

Low

Input Current Level

High

Low

Input Capacitance

Input Resistance

LOGIC INPUT (CSB)¹

Input Voltage Level

High

Full

−ꢀ

−100

+ꢀ

+100

μA

kΩ

Full

1.22

2.1

0.6

Low

Input Current Level

High

Low

Input Resistance

Input Capacitance

LOGIC INPUT (SCLK)²

Input Voltage Level

High

Full

−ꢀ

−80

+ꢀ

−4ꢀ

μA

kΩ

Full

1.22

2.1

0.6

Low

Rev. 0 | Page 6 of 36

1...3 4 567 8 9...36

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