AD6624ABC

更新时间： 2024-02-12 03:56:04

品牌	Logo	应用领域
亚德诺 - ADI		/
页数	文件大小	规格书
40页	510K
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AD6624ABC 数据手册

AD6624

MICROPROCESSOR PORT TIMING CHARACTERISTICS^{1, 2}

Test

AD6624AS

Typ

Parameter (Conditions)

Temp

Level

Min

Max

Unit

MICROPROCESSOR PORT, MODE INM (MODE = 0)

MODE INM Write Timing:

t_SC

t_HC

Control³to ↑CLK Setup Time

Full

5.5

1.0

8.0

–0.5

7.0

4.0

4 × t_CLK

Control³to ↑CLK Hold Time

t_HWR

t_SAM

t_HAM

t_DRDY

t_ACC

WR(RW) to RDY(DTACK) Hold Time

Address/Data to WR(RW) Setup Time

Address/Data to RDY(DTACK) Hold Time

WR(RW) to RDY(DTACK) Delay

WR(RW) to RDY(DTACK) High Delay

5 × t_CLK

9 × t_CLK

MODE INM Read Timing:

t_SC

t_HC

t_SAM

t_HAM

t_DRDY

t_ACC

Control³to ↑CLK Setup Time

Full

4.0

2.0

0.0

7.0

4.0

8 × t_CLK

Control³to ↑CLK Hold Time

Address to RD(DS) Setup Time

Address to Data Hold Time

RD(DS) to RDY(DTACK) Delay

RD(DS) to RDY(DTACK) High Delay

10 × t_CLK13 × t_CLK

MICROPROCESSOR PORT, MODE MNM (MODE = 1)

MODE MNM Write Timing:

t_SC

t_HC

Control³to ↑CLK Setup Time

Full

5.5

1.0

8.0

–0.5

7.0

4 × t_CLK

Control³to ↑CLK Hold Time

t_HDS

t_HRW

t_SAM

t_HAM

t_ACC

DS(RD) to DTACK(RDY) Hold Time

RW(WR) to DTACK(RDY) Hold Time

Address/Data to RW(WR) Setup Time

Address/Data to RW(WR) Hold Time

RW(WR) to DTACK(RDY) Low Delay

5 × t_CLK

9 × t_CLK

MODE MNM Read Timing:

t_SC

t_HC

t_SAM

t_HAM

t_ZD

Control³to ↑CLK Setup Time

Full

4.0

2.0

8.0

0.0

7.0

8 × t_CLK

Control³to ↑CLK Hold Time

Address to DS(RD) Setup Time

Address to Data Hold Time

Data Three-State Delay

t_ACC

DS(RD) to DTACK(RDY) Low Delay

10 × t_CLK13 × t_CLK

NOTES

¹All timing specifications valid over VDD range of 2.375 V to 2.675 V and VDDIO range of 3.0 V to 3.6 V.

²C_LOAD= 40 pF on all outputs unless otherwise specified.

³Specification pertains to control signals: RW, (WR), DS, (RD), CS.

Specifications subject to change without notice.

–5–

REV. B

1 2 3 456 7 8...40

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