Datasheet > AD6623

AD6623

更新时间： 2024-02-01 01:13:57

品牌	Logo	应用领域
亚德诺 - ADI		/
页数	文件大小	规格书
40页	374K
描述
4-Channel, 104 MSPS Digital Transmit Signal Processor TSP

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技术参数
数据手册

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AD6623 技术参数

是否无铅：	不含铅	是否Rohs认证：	符合
生命周期：	Active	零件包装代码：	QFP
包装说明：	FQFP,	针数：	128
Reach Compliance Code：	unknown	风险等级：	5.1
JESD-30 代码：	R-PQFP-G128	JESD-609代码：	e3
长度：	20 mm	湿度敏感等级：	3
功能数量：	1	端子数量：	128
最高工作温度：	85 °C	最低工作温度：	-40 °C
封装主体材料：	PLASTIC/EPOXY	封装代码：	FQFP
封装形状：	RECTANGULAR	封装形式：	FLATPACK, FINE PITCH
峰值回流温度（摄氏度）：	260	认证状态：	COMMERCIAL
座面最大高度：	3.4 mm	标称供电电压：	2.5 V
表面贴装：	YES	技术：	CMOS
电信集成电路类型：	TELECOM CIRCUIT	温度等级：	INDUSTRIAL
端子面层：	MATTE TIN	端子形式：	GULL WING
端子节距：	0.5 mm	端子位置：	QUAD
处于峰值回流温度下的最长时间：	40	宽度：	14 mm
Base Number Matches：	1

AD6623 数据手册

AD6623

Bit 6

Can be set through the serial port (see section on

serial word formats).

(0xn17) Power Ramp Length 0

This is the length of the ramp for mode 0, minus one.

Bits 3–0: Sets (N_RCF/L_RCF) –1

(0xn18) Power Ramp Length 1

This is the length of the ramp for mode 1, minus one. Setting

this to zero disables dual ramps.

(0xn0D) Channel Mode Control 2

Bits 7–6: Sets the RCF Coarse Scale as shown in Table XXIII.

(0xn19) Power Ramp Rest Time

Table XXIII. RCF Coarse Scale

This is the number of RCF output samples to rest for between a

ramp down and a ramp up.

Bit 7

Bit 6

RCF Coarse Scale (dB)

(0xn1A–0xn1F) Unused

–6

–12

–18

(0xn20–0xn3F) Data Memory

This group of registers contain the RCF Filter Data. See the RCF

section for additional details.

(0xn40–0xn17F) Power Ramp Coefficient Memory

This group of registers contain the Power Ramp Coefficients.

See the Power Ramp section for additional details.

Bit 5:

High enables the RCF phase equalizer.

Bits 4–0: Sets the serial clock divider (SDIV) that determines the

serial clock frequency based on the following equation.

(0xn80–0xn1FF) Coefficient Memory

This group of registers contain the RCF Filter Coefficients.

See the RCF section for additional details.

CLK

SDIV +1

f_SCLK

(28)

(0xn0E) Fine Scale Factor

PSEUDOCODE

Bits 15–2: Sets the RCF Fine Scale Factor as an unsigned number

representing the values (0,2). This register is shad-

owed for synchronization purposes. The shadow can

be read back directly, the Fine Scale Factor can not.

Bits 1–0: Reserved.

Write Pseudocode

Void Write_Micro(ext_address, int data);

Main()

{

/* This code shows the programming of the

NCO frequency register using the Write_Micro

function defined above. The variable

address is the External Address A[2:0] and

data is the value to be placed in the

external interface register.

(0xn0F) RCF Time Slot Hold-Off Counter

Bits 17–16: The Time Slot Sync Select bits are used to set which

sync pin will initiate a time slot sync sequence.

Bits 15–0: The Hold-Off Counter is used to synchronize the

change of RCF Fine Scale. See the Synchronization

section for a detailed explanation. If no synchroniza-

tion is required, this register should be set to 0.

Internal Address = 0x102, channel 1

(0xn10–0xn11) RCF Phase Equalizer Coefficients

See the RCF section for details.

/*Holding registers for NCO byte wide

access data*/

(0xn12–0xn15) FIR-PSK Magnitudes

See the RCF section for details.

int d3, d2, d1, d0;

/*NCO frequency word (32 bits wide)*/

NCO_FREQ=0x1BEFEFFF;

/*write Chan */

Write_Micro(7, 0x01);

/*write Addr */

Write_Micro(6,0x02);

/*write Byte 3*/

(0xn16) Serial Port Setup

Bits 7–6: Serial Data Frame Start Select

Title XXIV. Serial Port Setup

Bit 7

Bit 6

Serial Data Frame Start

d3=(NCO_FREQ & 0xFF02Y∞00)>>24;

Write_Micro(3,d3);

Internal Frame Request

External SDFI Pad

Previous Channel’s Frame End

/*write Byte 2*/

d2=(NCO_FREQ & 0xFF0000)>>16;

Write_Micro(2,d2);

/*write Byte 1*/

d1=(NCO_FREQ & 0xFF00)>>8;

Write_Micro(1,d1);

/*write Byte 0, Byte 0 is written last and

causes an internal write to occur*/

d0=NCO_FREQ & 0xFF;

Write_Micro(0,d0);

}

Bit 5:

Bit 4:

Bit 3:

Bit 2:

High means SDFO is a frame end, low means SDFO

is a frame request.

High selects serial slave mode. SCLK is an input in

serial slave mode.

High enables Fine Scaling through the Serial Port

(not available in FIR Mode).

High enables Serial Time Slot Syncs (not available

in FIR Mode).

Bit 1:

Bit 0:

High enables Power Ramp coefficient interpolation.

High enables the Power Ramp.

REV. 0

–35–

1...32 33 343536 37 38...40

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