AD660

更新时间： 2024-01-17 15:14:28

品牌	Logo	应用领域
亚德诺 - ADI		/
页数	文件大小	规格书
12页	428K
描述
Monolithic 16-Bit Serial/Byte DACPORT

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中文翻译

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技术参数
数据手册

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AD660 技术参数

Source Url Status Check Date：	2013-05-01 14:56:15.802	是否无铅：	含铅
是否Rohs认证：	不符合	生命周期：	Active
零件包装代码：	DIP	包装说明：	DIP, DIP24,.3
针数：	24	Reach Compliance Code：	not_compliant
ECCN代码：	3A001.A.2.C	HTS代码：	8542.39.00.01
风险等级：	5.16	Is Samacsys：	N
最大模拟输出电压：	10 V	最小模拟输出电压：	-10 V
转换器类型：	D/A CONVERTER	输入位码：	BINARY
输入格式：	SERIAL, PARALLEL, 8 BITS	JESD-30 代码：	R-GDIP-T24
JESD-609代码：	e0	最大线性误差 (EL)：	0.0061%
标称负供电电压：	-15 V	位数：	16
功能数量：	1	端子数量：	24
最高工作温度：	125 °C	最低工作温度：	-55 °C
封装主体材料：	CERAMIC, GLASS-SEALED	封装代码：	DIP
封装等效代码：	DIP24,.3	封装形状：	RECTANGULAR
封装形式：	IN-LINE	峰值回流温度（摄氏度）：	NOT APPLICABLE
电源：	5,+-15 V	认证状态：	Not Qualified
座面最大高度：	5.08 mm	最大稳定时间：	13 µs
标称安定时间 (tstl)：	2.5 µs	子类别：	Other Converters
最大压摆率：	18 mA	标称供电电压：	15 V
表面贴装：	NO	技术：	BICMOS
温度等级：	MILITARY	端子面层：	Tin/Lead (Sn63Pb37)
端子形式：	THROUGH-HOLE	端子节距：	2.54 mm
端子位置：	DUAL	处于峰值回流温度下的最长时间：	NOT APPLICABLE
宽度：	7.62 mm	Base Number Matches：	1

AD660 数据手册

AD660

DIGITAL CIRCUIT DETAILS

OUTPUT SETTLING AND GLITCH

The AD660 has several “dual-use” pins which allow flexible op-

eration while maintaining the lowest possible pin count and con-

sequently the smallest package size. The user should, therefore,

pay careful attention to the following information when applying

the AD660.

The AD660’s output buffer amplifier typically settles to within

0.0008% FS (1/2 LSB) of its final value in 8 µs for a full-scale

step. Figures 7a and 7b show settling for a full-scale and an LSB

step, respectively, with a 2 kΩ, 1000 pF load applied. The guar-

anteed maximum settling time at +25°C for a full-scale step is

13 µs with this load. The typical settling time for a 1 LSB step is

2.5 µs.

Data can be loaded into the AD660 in serial or byte mode as

described below.

The digital-to-analog glitch impulse is specified as 15 nV-s typi-

cal. Figure 7c shows the typical glitch impulse characteristic at

the code 011 . . . 111 to 100 . . . 000 transition when loading

the second rank register from the first rank register.

Serial Mode Operation is enabled by bringing SER (Pin 17)

low. This changes the function of DB0 (Pin 12) to that of the

serial input pin, SIN. It also changes the function of DB1 (Pin

11) to a control input that tells the AD660 whether the serial

data is going to be loaded MSB or LSB first.

600

In serial mode HBE and LBE are effectively disabled except for

LBE’s dual function which is to control whether the user wishes

to have the asynchronous clear function go to unipolar or bipo-

lar zero. (A low on LBE, when CLR is strobed, sends the DAC

output to unipolar zero, a high to bipolar zero.) The AD660

does not care about the status of HBE when in serial mode.

+10

400

200

–200

–400

–600

–10

Data is clocked into the input register on the rising edge of CS

as shown in Figure 1b. The data is then resident in the first rank

latch and can be loaded into the DAC latch by taking LDAC

high. This will cause the DAC to change to the appropriate out-

put value.

µs

a. –10 V to +10 V Full-Scale Step Settling

It should be noted that the clear function clears the DAC latch

but does not clear the first rank latch. Therefore, the data that

was previously resident in the first rank latch can be reloaded

simply by bringing LDAC high after the event that necessitated

CLR to be strobed has ended. Alternatively, new data can be

loaded into the first rank latch if desired.

600

400

200

The serial out pin (SOUT) can be used to daisy chain several

DACs together in multi-DAC applications to minimize the

number of isolators being used to cross an intrinsic safety bar-

rier. The first rank latch simply acts like a 16-bit shift register,

and repeated strobing of CS will shift the data out through

SOUT and into the next DAC. Each DAC in the chain will

require its own LDAC signal unless all of the DACs are to be

updated simultaneously.

–200

–400

–600

µs

b. LSB Step Settling

Byte Mode Operation is enabled simply by keeping SER high,

which configures DB0–DB7 as data inputs. In this mode HBE

and LBE are used to identify the data as either the high byte or

low byte of the 16-bit input word. (The user can load the data,

in any order, into the first rank latch.) As in the serial mode

case, the status of LBE, when CLR is strobed determines

whether the AD660 clears to unipolar or bipolar zero. There-

fore, when in byte mode, the user must take care to set LBE to

the desired status before strobing CLR. (In serial mode the user

can simply hardware LBE to the desired state.)

+10

–10

NOTE: CS is edge triggered. HBE, LBE and LDAC are level

triggered.

µs

c. D-to-A Glitch Impulse

Figure 7. Output Characteristics

REV. A

–9–

1...6 7 8910 11 12

中文翻译

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