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AD652JPZ-REEL PDF预览

AD652JPZ-REEL

更新时间: 2024-02-01 01:09:24
品牌 Logo 应用领域
亚德诺 - ADI 转换器模拟特殊功能转换器
页数 文件大小 规格书
28页 786K
描述
Monolithic Synchronous Voltage-to-Frequency Converter

AD652JPZ-REEL 技术参数

是否无铅: 含铅是否Rohs认证: 不符合
生命周期:Active零件包装代码:DIP
包装说明:CERDIP-16针数:16
Reach Compliance Code:unknown风险等级:5.65
Is Samacsys:N转换器类型:VOLTAGE TO FREQUENCY CONVERTER
JESD-30 代码:R-GDIP-T16JESD-609代码:e0
长度:19.05 mm最大线性误差 (EL):0.05%
湿度敏感等级:NOT APPLICABLE最大负输入电压:-5 V
最大负电源电压:-18 V最小负电源电压:-6 V
标称负供电电压:-15 V功能数量:1
端子数量:16最大工作频率:4 MHz
最高工作温度:125 °C最低工作温度:-55 °C
封装主体材料:CERAMIC, GLASS-SEALED封装代码:DIP
封装形状:RECTANGULAR封装形式:IN-LINE
峰值回流温度(摄氏度):NOT APPLICABLE最大正输入电压:5 V
认证状态:COMMERCIAL座面最大高度:5.08 mm
最大供电电压:18 V最小供电电压:6 V
标称供电电压:15 V表面贴装:NO
温度等级:MILITARY端子面层:TIN LEAD
端子形式:THROUGH-HOLE端子节距:2.54 mm
端子位置:DUAL处于峰值回流温度下的最长时间:NOT APPLICABLE
最大总误差:0.5%宽度:7.62 mm
Base Number Matches:1

AD652JPZ-REEL 数据手册

 浏览型号AD652JPZ-REEL的Datasheet PDF文件第5页浏览型号AD652JPZ-REEL的Datasheet PDF文件第6页浏览型号AD652JPZ-REEL的Datasheet PDF文件第7页浏览型号AD652JPZ-REEL的Datasheet PDF文件第9页浏览型号AD652JPZ-REEL的Datasheet PDF文件第10页浏览型号AD652JPZ-REEL的Datasheet PDF文件第11页 
AD652  
Another way to view this is that the output is a frequency of  
approximately one-quarter of the clock that has been phase  
modulated. A constant frequency can be thought of as  
The result of this synchronism is that the rate at which data may  
be extracted from the series bit stream produced by the SVFC is  
limited. The output pulses are typically counted during a fixed  
gate interval and the result is interpreted as an average  
frequency. The resolution of such a measurement is determined  
by the clock frequency and the gate time. For example, if the  
clock frequency is 4 MHz and the gate time is 4.096 ms, a  
maximum count of 8,192 is produced by a full-scale frequency  
of 2 MHz. Thus, the resolution is 13 bits.  
accumulating phase linearly with time at a rate equal to 2πf  
radians per second. Therefore, the average output frequency,  
which is slightly in excess of a quarter of the clock, requires  
phase accumulation at a certain rate. However, since the SVFC  
is running at exactly one-quarter of the clock, it does not  
accumulate enough phase (see Figure 7). When the difference  
between the required phase (average frequency) and the actual  
phase equals 2π, a step-in phase is taken where the deficit is  
made up instantaneously. The output frequency is then a steady  
carrier that has been phase modulated by a sawtooth signal (see  
Figure 7). The period of the sawtooth phase modulation is the  
time required to accumulate a 2π difference in phase between  
the required average frequency and one quarter of the clock  
frequency. The sawtooth phase modulation amplitude is 2π.  
OVERRANGE  
Since each reset pulse is only one clock period in length, the  
full-scale output frequency is equal to one-half the clock  
frequency. At full scale, the current steering switch spends half  
of the time on the summing junction; thus, an input current of  
0.5 mA can be balanced. In the case of an overrange, the output  
of the integrator op amp drifts in the negative direction and the  
output of the comparator remains high. The logic circuits  
simply settle into a divide-by-two of the clock state.  
PHASE  
2
π
π
EXPECTED  
PHASE  
2
ACTUAL PHASE  
TIME  
TIME  
φ
MOD (t)  
2π  
V
(t) = COS (2π × fAVE × t + φMOD (t))  
OUT  
AVERAGE  
CARRIER FREQUENCY  
PHASE  
MODULATION  
Figure 7. Phase Modulation  
Rev. C | Page 8 of 28  
 
 

AD652JPZ-REEL 替代型号

型号 品牌 替代类型 描述 数据表
AD652KPZ-REEL ADI

完全替代

Monolithic Synchronous Voltage-to-Frequency Converter
AD652JPZ ADI

完全替代

Monolithic Synchronous Voltage-to-Frequency Converter
AD652KP ADI

完全替代

Monolithic Synchronous Voltage-to-Frequency Converter

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