Datasheet > AD6439-2BS

AD6439-2BS

更新时间： 2024-01-27 12:44:27

品牌	Logo	应用领域
亚德诺 - ADI		电信电信集成电路
页数	文件大小	规格书
12页	113K
描述
IC SPECIALTY TELECOM CIRCUIT, PQFP128, PLASTIC, MQFP-128, Telecom IC:Other

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技术参数
数据手册

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AD6439-2BS 技术参数

生命周期：	Obsolete	零件包装代码：	QFP
包装说明：	FQFP,	针数：	128
Reach Compliance Code：	unknown	ECCN代码：	5A991.B.1
HTS代码：	8542.39.00.01	风险等级：	5.76
JESD-30 代码：	R-PQFP-G128	长度：	20 mm
功能数量：	1	端子数量：	128
最高工作温度：	85 °C	最低工作温度：	-40 °C
封装主体材料：	PLASTIC/EPOXY	封装代码：	FQFP
封装形状：	RECTANGULAR	封装形式：	FLATPACK, FINE PITCH
认证状态：	Not Qualified	座面最大高度：	2.35 mm
标称供电电压：	3.3 V	表面贴装：	YES
电信集成电路类型：	TELECOM CIRCUIT	温度等级：	INDUSTRIAL
端子形式：	GULL WING	端子节距：	0.5 mm
端子位置：	QUAD	宽度：	14 mm
Base Number Matches：	1

AD6439-2BS 数据手册

AD6439-2

35.328MH

TX_CLK

AEC0

AEC1

AEC2

AEC3

TX3

TX_AEC[15:0]

Figure 11. Tx_AEC MUX Bus in Normal Operation

DSP Port

2.208 MHz, the output bus rate 4.416 MHz and the Tx_CLK

signal 2.208 MHz. Data sent out is unsigned; however, the

AD6439-2 can be programmed to send out twos complement

binary data.

The AD6439-2 includes a DSP port consisting of a 14-bit address

bus A[13:0], a 16-bit data bus D[15:0], three bus control pins,

NRD, NWR, NCS, and a clock, DSP_CLK. The DSP port allows

a 2183 DSP to access the AD6439-2.

Note that Tx and AEC paths must always be in the same mode.

They are either both in normal mode, both in downsample mode,

or both in bypass mode.

ADDR[13:0]

DATA[15:0]

ADDR[13:0]

DATA[15:0]

ADC Interface

ADSP-2183

AD6439-2

The AD6439-2 includes an interface that accepts 16 bits

(Rx[15:0]) from an A/D converter. The sample rate is 8.832 MHz,

but if the Dec4 block is bypassed, the rate is only 2.208 MHz.

Signal Rx_CLK qualifies when the A/D converter needs to pro-

vide valid data. The AD6439-2 normally assumes that input data

is in unsigned binary format; however, it can also be programmed

to received twos complement binary data.

DSP_CLK

IOMSN

RDN

DSP_CLK

CSN

RDN

WRN

Figure 12. ADSP-2183 to AD6439-2 Interface

REV. 0

–11–

1...8 9 101112

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