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AD625SD

更新时间： 2024-02-15 21:45:52
品牌 Logo 应用领域
亚德诺 - ADI 仪表放大器放大器电路
页数 文件大小 规格书
15页 464K
描述
Programmable Gain Instrumentation Amplifier

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AD625SD 技术参数

Source Url Status Check Date：2013-05-01 14:56:15.434是否无铅： 含铅
是否Rohs认证： 不符合生命周期：Not Recommended
零件包装代码：DIP包装说明：DIP-16
针数：16Reach Compliance Code：not_compliant
ECCN代码：EAR99HTS代码：8542.31.00.01
风险等级：5.05Is Samacsys：N
放大器类型：INSTRUMENTATION AMPLIFIER最大平均偏置电流 (IIB)：0.05 µA
标称带宽 (3dB)：0.65 MHz最小共模抑制比：70 dB
最大输入失调电流 (IIO)：0.035 µA最大输入失调电压：200 µV
JESD-30 代码：R-CDIP-T16JESD-609代码：e0
长度：20.32 mm负供电电压上限：-18 V
标称负供电电压 (Vsup)：-15 V最大非线性：0.01%
功能数量：1端子数量：16
最高工作温度：125 °C最低工作温度：-55 °C
封装主体材料：CERAMIC, METAL-SEALED COFIRED封装代码：DIP
封装等效代码：DIP16,.3封装形状：RECTANGULAR
封装形式：IN-LINE峰值回流温度（摄氏度）：NOT SPECIFIED
电源：+-15 V认证状态：Not Qualified
座面最大高度：3.553 mm标称压摆率：5 V/us
子类别：Instrumentation Amplifier最大压摆率：5 mA
供电电压上限：18 V标称供电电压 (Vsup)：15 V
表面贴装：NO技术：BIPOLAR
温度等级：MILITARY端子面层：Tin/Lead (Sn63Pb37)
端子形式：THROUGH-HOLE端子节距：2.54 mm
端子位置：DUAL处于峰值回流温度下的最长时间：NOT SPECIFIED
最大电压增益：10000最小电压增益：1
标称电压增益：10宽度：7.62 mm
Base Number Matches：1

AD625SD 数据手册

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AD625  
THEORY OF OPERATION  
The diodes to the supplies are only necessary if input voltages  
outside of the range of the supplies are encountered. In higher  
gain applications where differential voltages are small, back-to-  
back Zener diodes and smaller resistors, as shown in Figure  
26b, provides adequate protection. Figure 26c shows low cost  
FETs with a maximum ON resistance of 300 Ω configured to offer  
input protection with minimal degradation to noise, (5.2 nV/√Hz  
compared to normal noise performance of 4 nV/√Hz).  
The AD625 is a monolithic instrumentation amplifier based on  
a modification of the classic three-op-amp approach. Monolithic  
construction and laser-wafer-trimming allow the tight matching  
and tracking of circuit components. This insures the high level  
of performance inherent in this circuit architecture.  
A preamp section (Q1–Q4) provides additional gain to A1 and  
A2. Feedback from the outputs of A1 and A2 forces the collec-  
tor currents of Q1–Q4 to be constant, thereby, impressing the  
input voltage across RG. This creates a differential voltage at the  
outputs of A1 and A2 which is given by the gain (2RF/RG + 1)  
times the differential portion of the input voltage. The unity  
gain subtracter, A3, removes any common-mode signal from the  
output voltage yielding a single ended output, VOUT, referred to  
the potential at the reference pin.  
During differential overload conditions, excess current will flow  
through the gain sense lines (Pins 2 and 15). This will have no  
effect in fixed gain applications. However, if the AD625 is being  
used in an SPGA application with a CMOS multiplexer, this  
current should be taken into consideration. The current capa-  
bilities of the multiplexer may be the limiting factor in allowable  
overflow current. The ON resistance of the switch should be  
included as part of RG when calculating the necessary input  
protection resistance.  
The value of RG is the determining factor of the transconduc-  
tance of the input preamp stage. As RG is reduced for larger  
gains the transconductance increases. This has three important  
advantages. First, this approach allows the circuit to achieve a  
very high open-loop gain of (3 × 108 at programmed gains ≥ 500)  
thus reducing gain related errors. Second, the gain-bandwidth  
product, which is determined by C3, C4, and the input trans-  
conductance, increases with gain, thereby, optimizing frequency  
response. Third, the input voltage noise is reduced to a value  
determined by the collector current of the input transistors  
(4 nV/√Hz).  
+VS  
FD333  
FD333  
1.4kꢀ  
+IN  
RF  
RG  
RF  
VOUT  
AD625  
1.4kꢀ  
–IN  
FD333  
FD333  
–VS  
INPUT PROTECTION  
Differential input amplifiers frequently encounter input voltages  
outside of their linear range of operation. There are two consid-  
erations when applying input protection for the AD625; 1) that  
continuous input current must be limited to less than 10 mA  
and 2) that input voltages must not exceed either supply by  
more than one diode drop (approximately 0.6 V @ 25°C).  
Figure 26a. Input Protection Circuit  
+V  
S
FD333  
FD333  
500ꢀ  
+IN  
R
F
Under differential overload conditions there is (RG + 100) Ω in  
series with two diode drops (approximately 1.2 V) between the  
plus and minus inputs, in either direction. With no external protec-  
tion and RG very small (i.e., 40 Ω), the maximum overload  
voltage the AD625 can withstand, continuously, is approximately  
2.5 V. Figure 26a shows the external components necessary to  
protect the AD625 under all overload conditions at any gain.  
1N5837A  
V
OUT  
R
G
AD625  
1N5837A  
R
F
500ꢀ  
–IN  
FD333  
FD333  
–V  
S
+V  
S
Figure 26b. Input Protection Circuit for G > 5  
+
V
–
50ꢂA  
50ꢂA  
B
+V  
S
FD333  
A1  
A2  
FD333  
10kꢀ  
C3  
C4  
SENSE  
+IN  
2kꢀ  
10kꢀ  
R
R
F
2N5952  
V
O
V
OUT  
AD625  
G
GAIN  
DRIVE  
GAIN  
10kꢀ  
50ꢀ  
10kꢀ  
DRIVE  
REF  
R
F
50ꢀ  
R
R
F
F
+IN  
Q1, Q3  
Q2, Q4  
–IN  
–IN  
R
G
2kꢀ  
FD333  
GAIN  
GAIN  
2N5952  
SENSE SENSE  
FD333  
50ꢂA  
50ꢂA  
–V  
S
–V  
S
Figure 26c. Input Protection Circuit  
Figure 25. Simplified Circuit of the AD625  
–8–  
REV. D  
1...567891011...15

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