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AD625SD

更新时间： 2024-02-01 14:21:25
品牌 Logo 应用领域
亚德诺 - ADI 仪表放大器放大器电路
页数 文件大小 规格书
15页 464K
描述
Programmable Gain Instrumentation Amplifier

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中文翻译

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AD625SD 技术参数

Source Url Status Check Date：2013-05-01 14:56:15.434是否无铅： 含铅
是否Rohs认证： 不符合生命周期：Not Recommended
零件包装代码：DIP包装说明：DIP-16
针数：16Reach Compliance Code：not_compliant
ECCN代码：EAR99HTS代码：8542.31.00.01
风险等级：5.05Is Samacsys：N
放大器类型：INSTRUMENTATION AMPLIFIER最大平均偏置电流 (IIB)：0.05 µA
标称带宽 (3dB)：0.65 MHz最小共模抑制比：70 dB
最大输入失调电流 (IIO)：0.035 µA最大输入失调电压：200 µV
JESD-30 代码：R-CDIP-T16JESD-609代码：e0
长度：20.32 mm负供电电压上限：-18 V
标称负供电电压 (Vsup)：-15 V最大非线性：0.01%
功能数量：1端子数量：16
最高工作温度：125 °C最低工作温度：-55 °C
封装主体材料：CERAMIC, METAL-SEALED COFIRED封装代码：DIP
封装等效代码：DIP16,.3封装形状：RECTANGULAR
封装形式：IN-LINE峰值回流温度（摄氏度）：NOT SPECIFIED
电源：+-15 V认证状态：Not Qualified
座面最大高度：3.553 mm标称压摆率：5 V/us
子类别：Instrumentation Amplifier最大压摆率：5 mA
供电电压上限：18 V标称供电电压 (Vsup)：15 V
表面贴装：NO技术：BIPOLAR
温度等级：MILITARY端子面层：Tin/Lead (Sn63Pb37)
端子形式：THROUGH-HOLE端子节距：2.54 mm
端子位置：DUAL处于峰值回流温度下的最长时间：NOT SPECIFIED
最大电压增益：10000最小电压增益：1
标称电压增益：10宽度：7.62 mm
Base Number Matches：1

AD625SD 数据手册

 浏览型号AD625SD的Datasheet PDF文件第9页浏览型号AD625SD的Datasheet PDF文件第10页浏览型号AD625SD的Datasheet PDF文件第11页浏览型号AD625SD的Datasheet PDF文件第12页浏览型号AD625SD的Datasheet PDF文件第14页浏览型号AD625SD的Datasheet PDF文件第15页 
AD625  
These capacitances may also be incorporated as part of the  
external input protection circuit (see section on Input Protec-  
tion). As a general practice every effort should be made to  
match the extraneous capacitance at Pins 15 and 2, and Pins 1  
and 16, to preserve high ac CMR.  
AD625  
–INPUT  
–GAIN  
SENSE  
20kꢀ  
–GAIN  
DRIVE  
C
S-OUT  
15.6kꢀ  
3.9kꢀ  
10kꢀ  
R
ON  
10kꢀ  
10kꢀ  
SOFTWARE PROGRAMMABLE GAIN AMPLIFIER  
An SPGA provides the ability to externally program precision  
gains from digital inputs. Historically, the problem in systems  
requiring electronic switching of gains has been the ON resis-  
tance (RON) of the multiplexer, which appears in series with the  
gain setting resistor RG. This can result in substantial gain errors  
and gain drifts. The AD625 eliminates this problem by making  
the gain drive and gain sense pins available (Pins 2, 15, 5, 12;  
see Figure 39). Consequently the multiplexer’s ON resistance is  
removed from the signal current path. This transforms the ON  
resistance error into a small nullable offset error. To clarify this  
point, an error budget analysis has been performed in Table II  
based on the SPGA configuration shown in Figure 39.  
C
C
OUT  
C
C
975kꢀ  
650kꢀ  
S
I
I
I
I
S
S
OUT  
C
12-BIT  
DAS  
–
V
S
V
IN  
S-OUT  
+
975kꢀ  
3.9kꢀ  
R
ON  
OUT  
S
10kꢀ  
+GAIN  
DRIVE  
OUT  
15.6kꢀ  
+GAIN  
SENSE  
20kꢀ  
+INPUT  
Figure 39. SPGA with Multiplexer Error Sources  
Figure 39 shows a complete SPGA feeding a 12-bit DAS with a  
0 V–10 V input range. This configuration was used in the error  
budget analysis shown in Table II. The gain used for the RTI  
calculations is set at 16. As the gain is changed, the ON resis-  
tance of the multiplexer and the feedback resistance will change,  
which will slightly alter the values in the table.  
AD7502  
TTL/DTL TO CMOS LEVEL TRANSLATOR  
V
V
A0  
A1  
SS  
DECODER/DRIVER  
DD  
GND  
E
N
Table II. Errors Induced by Multiplexer to an SPGA  
3.9kꢀ 975ꢀ 650ꢀ 975ꢀ 3.9kꢀ  
Induced  
Error  
Specifications  
AD625C AD7520KN Calculation  
Voltage Offset  
Induced RTI  
20kꢀ  
15.6kꢀ  
15.6kꢀ  
20kꢀ  
RTI Offset Gain Sense Switch  
40 nA × 170 Ω =  
6.8 µV  
6.8 µV  
+INPUT  
–INPUT  
Voltage  
Offset  
Current  
40 nA  
Resistance  
170 Ω  
1
2
3
4
5
6
7
16  
15  
14  
13  
12  
11  
10  
+GAIN  
–GAIN  
SENSE  
SENSE  
RTI Offset Gain Sense Differential 60 nA × 6.8 Ω =  
0.41 µV  
Voltage  
Current  
60 nA  
Switch  
Resistance  
6.8 Ω  
0.41 µV  
RTI NULL  
RTO NULL  
–V  
+V  
S
S
RTI NULL  
RTO NULL  
A1  
A2  
RTO Offset Feedback Differential 2 (0.2 nA × 20 kΩ) 0.5 µV  
Voltage Resistance Leakage = 8 µV/16  
Current (IS)2  
+GAIN DRIVE  
–GAIN DRIVE  
NC  
20 kΩ1  
10kꢀ  
10kꢀ  
V
OUT  
REF  
+0.2 nA  
10kꢀ  
10kꢀ  
A3  
–0.2 nA  
+V  
S
8
9
–V  
S
AD625  
RTO Offset Feedback Differential 2 (1 nA × 20 kΩ)  
Voltage Resistance Leakage = 40 µV/16  
20 kΩ1  
Current  
2.5 µV  
Figure 38. SPGA in a Gain of 16  
2
(IOUT  
)
Figure 38 shows an AD625 based SPGA with possible gains of  
1, 4, 16, 64. RG equals the resistance between the gain sense  
lines (Pins 2 and 15) of the AD625. In Figure 38, RG equals  
the sum of the two 975 Ω resistors and the 650 Ω resistor, or  
2600 Ω. RF equals the resistance between the gain sense and the  
gain drive pins (Pins 12 and 15, or Pins 2 and 5), that is RF  
equals the 15.6 kΩ resistor plus the 3.9 kΩ resistor, or 19.5 kΩ.  
The gain, therefore equals:  
+1 nA  
–1 nA  
Total error induced by a typical CMOS multiplexer  
to an SPGA at +25°C  
10.21 ꢂA  
NOTES  
1The resistor for this calculation is the user-provided feedback resistance (RF).  
20 kΩ is recommended value (see Resistor Programmable Gain Amplifier section).  
2The leakage currents (IS and IOUT) will induce an offset voltage, however, the offset  
will be determined by the difference between the leakages of each “half’’ of the  
differential multiplexer. The differential leakage current is multiplied by the  
feedback resistance (see Note 1), to determine offset voltage. Because differential  
leakage current is not a parameter specified on multiplexer data sheets, the most  
extreme difference (one most positive and one most negative) was used for the  
calculations in Table II. Typical performance will be much better.  
2RF  
2(19.5kΩ)  
(2.6kΩ)  
+1=  
+1=16  
RG  
As the switches of the differential multiplexer proceed synchro-  
nously, RG and RF change, resulting in the various programmed  
gain settings.  
**The frequency response and settling will be affected by the ON resistance and  
internal capacitance of the multiplexer. Figure 40 shows the settling time vs.  
ON resistance at different gain settings for an AD625 based SPGA.  
**Switch resistance and leakage current errors can be reduced by using relays.  
REV. D  
–13–  
1...101112131415

中文翻译

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AD625SD 替代型号

型号 品牌 替代类型 描述 数据表
AD625BD/+ ADI

完全替代

 IC INSTRUMENTATION AMPLIFIER, 50 uV OFFSET-MAX, 0.65 MHz BAND WIDTH, CDIP16, CERAMIC, DIP-
AD625ADZ ADI

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 Programmable Gain Instrumentation Amplifier
AD625CDZ ADI

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 Programmable Gain Instrumentation Amplifier

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AD625SE883B ETC

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 		MICROCIRCUIT, LINEAR, PROGRAMMABLE GAIN MICROCIRCUIT, LINEAR, PROGRAMMABLE GAIN MONOLITHIC
AD626 ADI

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