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AD5940BCBZ-RL

更新时间： 2024-01-29 09:07:17
品牌 Logo 应用领域
亚德诺 - ADI /
页数 文件大小 规格书
130页 1952K
描述
High Precision, Impedance, and Electrochemical Front End

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中文翻译

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AD5940BCBZ-RL 技术参数

是否无铅： 含铅是否Rohs认证： 符合
生命周期：Active包装说明：WLCSP-56
针数：56Reach Compliance Code：compliant
风险等级：5.81模拟集成电路 - 其他类型：ANALOG CIRCUIT
JESD-30 代码：R-PBGA-B56长度：4.16 mm
功能数量：1端子数量：56
最高工作温度：85 °C最低工作温度：-40 °C
封装主体材料：PLASTIC/EPOXY封装代码：VFBGA
封装形状：RECTANGULAR封装形式：GRID ARRAY, VERY THIN PROFILE, FINE PITCH
座面最大高度：0.55 mm最大供电电压 (Vsup)：3.6 V
最小供电电压 (Vsup)：2.8 V标称供电电压 (Vsup)：3.3 V
表面贴装：YES温度等级：INDUSTRIAL
端子形式：BALL端子节距：0.4 mm
端子位置：BOTTOM宽度：3.56 mm

AD5940BCBZ-RL 数据手册

 浏览型号AD5940BCBZ-RL的Datasheet PDF文件第5页浏览型号AD5940BCBZ-RL的Datasheet PDF文件第6页浏览型号AD5940BCBZ-RL的Datasheet PDF文件第7页浏览型号AD5940BCBZ-RL的Datasheet PDF文件第9页浏览型号AD5940BCBZ-RL的Datasheet PDF文件第10页浏览型号AD5940BCBZ-RL的Datasheet PDF文件第11页 
AD5940  
Data Sheet  
Parameter  
Symbol Min  
Typ  
Max  
Unit  
Test Conditions/Comments  
Three-Resistor Star Cell  
Accuracy  
R1 = R2 = R3 = 2.2 Ω (see Figure 14); 0.1 Hz to  
200 kHz  
Magnitude  
Phase  
0.ꢀ  
0.ꢀ  
%
Degrees  
Accuracy  
R1 = R2 = R3 = 100 Ω connected (see Figure 14);  
0.1 kHz to 200 kHz  
Magnitude  
Phase  
0.2  
0.2  
%
Degrees  
With High Bandwidth Loop, ꢀ0 kHz,  
4-Wire Isolated  
For Z = 1 kΩ (0.1% tolerant resistor); excitation  
frequency = ꢀ0 kHz; sine amplitude = 0.6 V p-p;  
RTIA = 1 kΩ; CTIA = 32 pF; Isolation Capacitor 1  
(CISO1) = 1ꢀ nF; Isolation Capacitor 2 (CISO2) =  
Isolation Capacitor 3 (CISO3) = Isolation Capacitor 4  
(CISO4) = 470 nF; current-limiting resistor (RLIMIT) =  
1 kΩ  
Accuracy  
Device to device repeatability for three devices  
at ꢀ0 kHz  
Magnitude  
Phase  
0.26  
1
%
Percentage error  
Degrees  
With Low Bandwidth Loop  
For Z = 100 kΩ; excitation frequency = 100 Hz; sine  
amplitude = 1.1 V p-p; RTIA = 100 kΩ; CTIA = 100 nF;  
CISO1 = 1ꢀ nF; CISO2 = 470 nF; RLIMIT = 1000 Ω  
Frequency Range  
Accuracy  
1
300  
Hz  
Device to device repeatability for three devices  
at 100 Hz  
Magnitude  
Precision  
Magnitude  
0.3  
%
Ω
Percentage error  
6.ꢀ3  
Standard deviation  
High Speed Loop  
See Figure 14; valid for impedance  
spectroscopy, voltammetry, and pulse tests  
Allowed External Load  
Capacitance1  
100  
pF  
R2 + R3 ≤ 100 Ω; R1 ≤ 100 Ω  
ꢀ0  
40  
pF  
pF  
R2 + R3 ≤ ꢀ00 Ω; R1 ≤ 100 Ω  
R2 + R3 ≤ 1600 Ω; R1 ≤ 800 Ω; frequency ≥ 1 kHz  
Excitation Amplifier Bandwidth  
Impedance Frequency Range  
LOW POWER TIA AND POTENTIOSTAT  
Input Bias Current1  
3
MHz  
200000 Hz  
0.01ꢀ  
TIA Amplifier, SE0 Pin  
80  
20  
ꢀ0  
1
200  
1ꢀ0  
1ꢀ0  
pA  
pA  
μV  
μV/°C  
PA  
Offset Voltage1  
Offset Voltage Drift vs. Temperature  
Noise  
Unity-gain mode; V p-p in 0.1 Hz to 10 Hz range  
Normal mode (LPTIACON0, Bit 2 = 0)  
Half power mode (LPTIACON0, Bit 2 = 1)  
Normal mode (LPTIACON0, Bits[4:3] = 00); from  
CE0  
High current mode (LPTIACON0, Bits[4:3] = 01  
or 11 from CE0  
1.6  
2
μV  
μV  
μA  
Potentiostat Source/Sink Current1  
−7ꢀ0  
−3  
+7ꢀ0  
+3  
mA  
DC PSRR  
70  
dB  
At RE0 pin; RTIA = 2ꢀ6 kΩ; RLOAD = 10 Ω  
Input Common-Mode Range1  
300  
300  
300  
AVDD – mV  
600  
AVDD – mV  
400  
AVDD − mV  
400  
Output Voltage Range1  
Normal mode (LPTIACON0, Bits[4:3] = 00;  
sink/source = 7ꢀ0 μA  
High current mode (LPTIACON0, Bits[4:3] = 01 or  
11); sink/source = 3 mA  
Overcurrent Limit Protection  
20  
mA  
Amplifiers try to limit source/sink current to this  
value via internal clamp  
Rev. 0 | Page 8 of 130  
1...567891011...130

中文翻译

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