AD5757

更新时间： 2024-01-26 16:58:19

品牌	Logo	应用领域
亚德诺 - ADI		/
页数	文件大小	规格书
44页	950K
描述
Quad-Channel, 12-Bit, Serial Input, 4 mA to 20 mA Output

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AD5757 技术参数

生命周期：	Obsolete	零件包装代码：	QFN
包装说明：	,	针数：	64
Reach Compliance Code：	unknown	风险等级：	5.78
Is Samacsys：	N	转换器类型：	D/A CONVERTER
JESD-30 代码：	S-XQCC-N64	位数：	16
端子数量：	64	封装主体材料：	UNSPECIFIED
封装形状：	SQUARE	封装形式：	CHIP CARRIER
认证状态：	Not Qualified	表面贴装：	YES
端子形式：	NO LEAD	端子位置：	QUAD
Base Number Matches：	1

AD5757 数据手册

AD5737

Data Sheet

AC PERFORMANCE CHARACTERISTICS

AV_DD= V_{BOOST_x}= 15 V; DV_DD= 2.7 V to 5.5 V; AV_CC= 4.5 V to 5.5 V; dc-to-dc converter disabled; AGND = DGND = GNDSW_x= 0 V;

REFIN = 5 V; R_L= 300 Ω; all specifications T_MINto T_MAX, unless otherwise noted.

Table 2.

Parameter¹

Min

Typ

Max

Unit

Test Conditions/Comments

DYNAMIC PERFORMANCE, CURRENT

OUTPUT

Output Current Settling Time

µs

To 0.1% FSR, 0 mA to 24 mA range

See Test Conditions/Comments

For settling times when using the dc-to-dc con-

verter, see Figure 25, Figure 26, and Figure 27

Output Noise (0.1 Hz to 10 Hz

Bandwidth)

Output Noise Spectral Density

0.15

0.5

LSB p-p

nA/√Hz

12-bit LSB, 0 mA to 24 mA range

Measured at 10 kHz, midscale output, 0 mA

to 24 mA range

¹Guaranteed by design and characterization; not production tested.

TIMING CHARACTERISTICS

AV_DD= V_{BOOST_x}= 15 V; DV_DD= 2.7 V to 5.5 V; AV_CC= 4.5 V to 5.5 V; dc-to-dc converter disabled; AGND = DGND = GNDSW_x= 0 V;

REFIN = 5 V; R_L= 300 Ω; all specifications T_MINto T_MAX, unless otherwise noted.

Table 3.

Parameter^{1, 2, 3}

Limit at T_MIN, T_MAX

Unit

Description

t₁

t₂

t₃

t₄

t₅

t₆

t₇

t₈

t₉

198

ns min

µs min

SCLK cycle time

SCLK high time

SCLK low time

SYNC falling edge to SCLK falling edge setup time

24th/32nd SCLK falling edge to SYNC rising edge (see Figure 53)

SYNC high time

Data setup time

Data hold time

SYNC rising edge to LDAC falling edge (all DACs updated or any channel has

digital slew rate control enabled)

µs min

ns min

ns max

µs max

ns min

µs max

ns max

SYNC rising edge to LDAC falling edge (single DAC updated)

t₁₀

t₁₁

t₁₂

t₁₃

t₁₄

t₁₅

t₁₆

LDAC pulse width low

500

LDAC falling edge to DAC output response time

DAC output settling time

CLEAR high time

See Table 2

CLEAR activation time

SCLK rising edge to SDO valid

SYNC rising edge to DAC output response time (LDAC = 0)

All DACs updated

Single DAC updated

LDAC falling edge to SYNC rising edge

RESET pulse width

500

800

µs min

ns min

t₁₇

t₁₈

t₁₉

SYNC high to next SYNC low (digital slew rate control enabled)

All DACs updated

Single DAC updated

µs min

¹Guaranteed by design and characterization; not production tested.

²All input signals are specified with t_RISE= t_FALL= 5 ns (10% to 90% of DV_DD) and timed from a voltage level of 1.2 V.

³See Figure 3, Figure 4, Figure 5, and Figure 6.

LDAC

This specification applies if

is held low during the write cycle; otherwise, see t₉.

Rev. B | Page 6 of 44

1...3 4 567 8 9...44

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