Quad Channel, 16-Bit,
Serial Input, 4 mA to 20 mA Output DAC,
Dynamic Power Control, HART Connectivity
AD5757
a dc-to-dc boost converter optimized for minimum on-chip
power dissipation.
FEATURES
16-bit resolution and monotonicity
Dynamic power control for thermal management
or external PMOS mode
Each channel has a corresponding CHART pin so that HART
signals can be coupled onto the current output of the AD5757.
Current output ranges: 0 mA to 20 mA, 4 mA to 20 mA,
or 0 mA to 24 mA
0.0ꢀ5 total unadjusted error ꢁTUEꢂ maximum
User programmable offset and gain
On-chip diagnostics
The part uses a versatile 3-wire serial interface that operates at
clock rates of up to 30 MHz and is compatible with standard
SPI, QSPI™, MICROWIRE™, DSP, and microcontroller interface
standards. The interface also features optional CRC-8 packet
error checking, as well as a watchdog timer that monitors
activity on the interface.
On-chip reference ꢁ 10 ppmꢃ/C maximumꢂ
−40/C to +10ꢀ/C temperature range
PRODUCT HIGHLIGHTS
APPLICATIONS
1. Dynamic power control for thermal management.
2. 16-bit performance.
3. Multichannel.
Process control
Actuator control
PLCs
4. HART compliant.
HART network connectivity
COMPANION PRODUCTS
GENERAL DESCRIPTION
Product Family: ADꢀ7ꢀꢀ-1, ADꢀ7ꢀꢀ
The AD5757 is a quad, current output DAC that operates with a
power supply range from 10.8 V to 33 V. On-chip dynamic
power control minimizes package power dissipation by regulat-
ing the voltage on the output driver from 7.4 V to 29.5 V using
External References: ADR44ꢀ, ADR02
Digital Isolators: ADuM1410, ADuM1411
Power: ADP2302, ADP2303
Additional companion products on the AD5757 product page
FUNCTIONAL BLOCK DIAGRAM
AV
CC
5.0V
AV
DD
AGND +15V
SW
x
V
BOOST_x
DV
7.4V TO 29.5V
DD
DGND
LDAC
DC-TO-DC
CONVERTER
SCLK
SDIN
DIGITAL
INTERFACE
SYNC
I
OUT_x
SDO
CLEAR
FAULT
R
+
DAC A
SET_x
CURRENT AND
VOLTAGE
OUTPUT RANGE
SCALING
CHARTx
ALERT
AD1
GAIN REG A
OFFSET REG A
AD0
DAC CHANNEL A
REFOUT
REFIN
REFERENCE
DAC CHANNEL B
DAC CHANNEL C
DAC CHANNEL D
AD5757
NOTES
1. x = A, B, C, AND D.
Figure 1.
Rev. A
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