AD5755BCPZX

更新时间： 2024-02-08 01:28:43

品牌	Logo	应用领域
亚德诺 - ADI		转换器数模转换器功率控制
页数	文件大小	规格书
34页	699K
描述
Quad Channel, 16-Bit, Serial Input, 4-20mA & Voltage Output DAC, Dynamic Power Control

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技术参数
数据手册

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AD5755BCPZX 技术参数

生命周期：	Obsolete	零件包装代码：	QFN
包装说明：	,	针数：	64
Reach Compliance Code：	unknown	风险等级：	5.75
转换器类型：	D/A CONVERTER	JESD-30 代码：	S-XQCC-N64
位数：	16	端子数量：	64
封装主体材料：	UNSPECIFIED	封装形状：	SQUARE
封装形式：	CHIP CARRIER	认证状态：	Not Qualified
表面贴装：	YES	端子形式：	NO LEAD
端子位置：	QUAD	Base Number Matches：	1

AD5755BCPZX 数据手册

Preliminary Technical Data

AD5755/AD5735

Parameter¹

Gain TC²

Min

Typ

TBD

Max

Unit

ppm FSR/°C

% FSR

ppm FSR/°C

Test Conditions/Comments

−TBD

−0.12

−TBD

+TBD

+0.12

+TBD

Full-Scale Error

T_A= 25°C

Full-Scale TC²

OUTPUT CHARACTERISTICS²

Current Loop Compliance Voltage

AVDD - V max

2.5

Output Current Drift vs. Time

ppm FSR

Drift after 500 hours, T_J= 150°C

(this is included in the TUE specifications)

ppm FSR

Ω max

Drift after 1000 hours, T_J= 150°C

(this is included in the TUE specifications)

Chosen such that compliance is not exceeded. Plus

see graph on load vs. AVcc and DCDC switching freq.

Resistive Load

Inductive Load

DC PSRR

See

Com

men

See

Com

men

H max

Will need appropriate cap at higher inductance values.

See Page X of Datasheet.

TBD

µA/V

MΩ

TBD

5.05

Output Impedance

REFERENCE INPUT/OUTPUT

Reference Input²

Reference Input Voltage

DC Input Impedance

Reference Output

4.95

TBD

V nom

MΩ min

For specified performance

T_A= 25°C

Output Voltage

Reference TC^2,3

Output Noise (0.1 Hz to 10 Hz)²

Noise Spectral Density²

Output Voltage Drift vs. Time²

4.998

-10

5.002

TBD

ppm/°C

µV p-p typ

nV/√Hz typ

ppm

At 10 kHz

Drift after 500 hours, T_J= 150°C

ppm

Drift after 1000 hours, T_J= 150°C

Capacitive Load²

Load Current

TBD

Short Circuit Current

Line Regulation²

Load Regulation²

Thermal Hysteresis²

DC-DC

TBD

ppm/V

ppm/mA

ppm

SWITCH

SWITCH On Resistance

SWITCH Leakage Current

Peak Current Limit

OSCILLATOR

Oscillator Frequency

Maximum Duty Cycle

DIGITAL INPUTS²

V_IH, Input High Voltage

V_IL, Input Low Voltage

0.5

TBD

0.8

ohm

VIN=TBD, IOUT=TBD, RLOAD=TBD

JEDEC compliant

TBD

0.8

KHz

Rev. PrG | Page 5 of 34

1 2 3 456 7 8...34

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