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AD5751ACPZ-REEL7

更新时间： 2024-01-25 05:51:01
品牌 Logo 应用领域
亚德诺 - ADI 驱动接口集成电路
页数 文件大小 规格书
32页 609K
描述
Industrial I/V Output Driver, Single-Supply, 55 V Maximum Supply, Programmable Ranges

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AD5751ACPZ-REEL7 技术参数

是否无铅： 含铅是否Rohs认证： 符合
生命周期：Active零件包装代码：QFN
包装说明：HVQCCN, LCC32,.2SQ,20针数：32
Reach Compliance Code：compliantECCN代码：EAR99
HTS代码：8542.39.00.01风险等级：1.64
内置保护：OVER CURRENT接口集成电路类型：BUFFER OR INVERTER BASED PERIPHERAL DRIVER
JESD-30 代码：S-XQCC-N32JESD-609代码：e3
长度：5 mm湿度敏感等级：1
功能数量：1端子数量：32
最高工作温度：105 °C最低工作温度：-40 °C
输出电流流向：SINK标称输出峰值电流：0.015 A
封装主体材料：UNSPECIFIED封装代码：HVQCCN
封装等效代码：LCC32,.2SQ,20封装形状：SQUARE
封装形式：CHIP CARRIER, HEAT SINK/SLUG, VERY THIN PROFILE峰值回流温度（摄氏度）：225
电源：3/5,12/55 V认证状态：Not Qualified
座面最大高度：1 mm子类别：Peripheral Drivers
最大供电电压：5.5 V最小供电电压：2.7 V
标称供电电压：3 V表面贴装：YES
温度等级：INDUSTRIAL端子面层：Matte Tin (Sn)
端子形式：NO LEAD端子节距：0.5 mm
端子位置：QUAD处于峰值回流温度下的最长时间：NOT SPECIFIED
宽度：5 mmBase Number Matches：1

AD5751ACPZ-REEL7 数据手册

 浏览型号AD5751ACPZ-REEL7的Datasheet PDF文件第7页浏览型号AD5751ACPZ-REEL7的Datasheet PDF文件第8页浏览型号AD5751ACPZ-REEL7的Datasheet PDF文件第9页浏览型号AD5751ACPZ-REEL7的Datasheet PDF文件第11页浏览型号AD5751ACPZ-REEL7的Datasheet PDF文件第12页浏览型号AD5751ACPZ-REEL7的Datasheet PDF文件第13页 
AD5751  
Data Sheet  
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS  
SDO/VFAULT 1  
CLRSEL 2  
CLEAR 3  
DVCC 4  
GND 5  
SYNC/RSET 6  
SCLK/OUTEN 7  
SDIN/R0 8  
24 VSENSE+  
23 VOUT  
22 GND  
AD5751  
TOP VIEW  
(Not to Scale)  
21 GND  
20 COMP1  
19 COMP2  
18 IOUT  
17 AVDD  
NOTES  
1. NC = NO CONNECT. CAN BE TIED TO GND.  
2. THE EXPOSED PADDLE IS TIED TO GND.  
Figure 4. Pin Configuration  
Table 5. Pin Function Descriptions  
Pin No.  
Mnemonic  
Description  
1
SDO/VFAULT  
Serial Data Output (SDO). In software mode, this pin is used to clock data from the input shift register in  
readback mode. Data is clocked out on the rising edge of SCLK and is valid on the falling edge of SCLK.  
This pin is a CMOS output.  
Short-Circuit Fault Alert (VFAULT). In hardware mode, this pin acts as a short-circuit fault alert pin and is  
asserted low when a short-circuit error is detected. This pin is an open-drain output and must be  
connected to a pull-up resistor.  
2
3
CLRSEL  
CLEAR  
In hardware or software mode, this pin selects the clear value, either zero-scale or midscale code. In  
software mode, this pin is implemented as a logic OR with the internal CLRSEL bit.  
Active High Input. Asserting this pin sets the output current/voltage to zero-scale code or midscale code  
of range selected (user-selectable). CLEAR is a logic OR with the internal clear bit. See the Asynchronous  
Clear (CLEAR) section for more details.  
In software mode, during power-up, the CLEAR pin level determines the power-on condition of the  
voltage channel, which can be active 0 V or tristate.  
4
5
6
DVCC  
GND  
SYNC/RSET  
Digital Power Supply.  
Ground Connection.  
Positive Edge-Sensitive Latch (SYNC). In software mode, a rising edge parallel loads the input shift  
register data into the AD5751, also updating the output.  
Resistor Select (RSET). In hardware mode, this pin selects whether the internal or the external current  
sense resistor is used.  
If RSET = 0, the external sense resistor is chosen.  
If RSET = 1, the internal sense resistor is chosen.  
7
8
9
SCLK/OUTEN  
SDIN/R0  
Serial Clock Input (SCLK). In software mode, data is clocked into the input shift register on the falling  
edge of SCLK. This pin operates at clock speeds up to 50 MHz.  
Output Enable (OUTEN). In hardware mode, this pin acts as an output enable pin.  
Serial Data Input (SDIN). In software mode, data must be valid on the falling edge of SCLK.  
Range Decode Bit (R0). In hardware mode, this pin, in conjunction with R1, R2, and R3, selects the output  
current/voltage range setting on the part.  
AD2/R1  
Device Addressing Bit (AD2). In software mode, this pin, in conjunction with AD0 and AD1, allows up to  
eight devices to be addressed on one bus.  
Range Decode Bit (R1). In hardware mode, this pin, in conjunction with R0, R2, and R3, selects the output  
current/voltage range setting on the part.  
Rev. D | Page 10 of 32  
 
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