Datasheet > AD5684BCPZ-RL7

AD5684BCPZ-RL7

更新时间： 2024-11-27 20:46:43

品牌	Logo	应用领域
亚德诺 - ADI		转换器
页数	文件大小	规格书
27页	739K
描述
Quad, 12-Bit nanoDAC+ with SPI Interface

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数据手册

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AD5684BCPZ-RL7 数据手册

Quad, 16-/12-Bit nanoDAC+

with SPI Interface

Data Sheet

AD5686/AD5684

FEATURES

FUNCTIONAL BLOCK DIAGRAM

GND

REF

High relative accuracy (INL): 2 LSB maximum @ 16 bits

Tiny package: 3 mm × 3 mm, 16-lead LFCSP

Total unadjusted error (TUE): 0.1% of FSR maximum

Offset error: 1.5 mV maximum

Gain error: 0.1% of FSR maximum

High drive capability: 20 mA, 0.5 V from supply rails

User selectable gain of 1 or 2 (GAIN pin)

Reset to zero scale or midscale (RSTSEL pin)

1.8 V logic compatibility

AD5686/AD5684

LOGIC

STRING

DAC A

INPUT

DAC

OUT

SCLK

SYNC

SDIN

SDO

BUFFER

STRING

DAC B

INPUT

DAC

STRING

DAC C

INPUT

DAC

50 MHz SPI with readback or daisy chain

Low glitch: 0.5 nV-sec

STRING

DAC D

INPUT

DAC

POWER-ON

RESET

GAIN

×1/×2

POWER-

DOWN

LOGIC

Low power: 1.8 mW at 3 V

2.7 V to 5.5 V power supply

−40°C to +105°C temperature range

LDAC RESET

RSTSEL

GAIN

Figure 1.

APPLICATIONS

Digital gain and offset adjustment

Programmable attenuators

Process control (PLC I/O cards)

Industrial automation

Data acquisition systems

GENERAL DESCRIPTION

The AD5686/AD5684, members of the nanoDAC+™ family, are

low power, quad, 16-/12-bit buffered voltage output DACs.

The devices include a gain select pin giving a full-scale output

of 2.5 V (gain = 1) or 5 V (gain = 2). All devices operate from

a single 2.7 V to 5.5 V supply, are guaranteed monotonic by

design, and exhibit less than 0.1% FSR gain error and 1.5 mV

offset error performance. The devices are available in a 3 mm

× 3 mm LFCSP and a TSSOP package.

Table 1. Quad nanoDAC+ Devices

Interface Reference 16-Bit

14-Bit

12-Bit

SPI

I²C

Internal

External

Internal

External

AD5686R

AD5686

AD5696R

AD5696

AD5685R AD5684R

AD5684

AD5695R AD5694R

AD5694

PRODUCT HIGHLIGHTS

The AD5686/AD5684 also incorporate a power-on reset circuit

and a RSTSEL pin that ensures that the DAC outputs power up

to zero scale or midscale and remain at that level until a valid

write takes place. Each part contains a per-channel power-down

feature that reduces the current consumption of the device to

4 µA at 3 V while in power-down mode.

1. High Relative Accuracy (INL).

AD5686 (16-bit): 2 LSB maximum

AD5684 (12-bit): 1 LSB maximum

2. Excellent DC Performance.

Total unadjusted error: 0.1% of FSR maximum

Offset error: 1.5 mV maximum

The AD5686/AD5684 employ a versatile SPI interface that

operates at clock rates up to 50 MHz, and all devices contain

a V_LOGICpin intended for 1.8 V/3 V/5 V logic.

Gain error: 0.1% of FSR maximum

3. Two Package Options.

3 mm × 3 mm, 16-lead LFCSP

16-lead TSSOP

Rev. C

Document Feedback

Information furnished by Analog Devices is believed to be accurate and reliable. However, no

responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other

rightsof third parties that may result fromits use. Specifications subject to change without notice. No

license is granted by implication or otherwise under any patent or patent rights of Analog Devices.

Trademarks andregisteredtrademarks are the property of their respective owners.

One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.

Technical Support

www.analog.com

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与AD5684BCPZ-RL7相关器件

型号	品牌	获取价格	描述	数据表
AD5684BRUZ	ADI	获取价格	Quad, 12-Bit nanoDAC+ with SPI Interface
AD5684BRUZ-RL7	ADI	获取价格	Quad, 12-Bit nanoDAC+ with SPI Interface
AD5684R	ADI	获取价格	Quad 16-/14-/12-Bit nanoDAC
AD5684RARUZ	ADI	获取价格	Quad, 16-/14-/12-Bit nanoDAC
AD5684RARUZ-RL7	ADI	获取价格	Quad, 16-/14-/12-Bit nanoDAC
AD5684RBCPZ-RL7	ADI	获取价格	Quad, 16-/14-/12-Bit nanoDAC
AD5684RBRUZ	ADI	获取价格	Quad, 16-/14-/12-Bit nanoDAC
AD5684RBRUZ-RL7	ADI	获取价格	Quad, 16-/14-/12-Bit nanoDAC
AD5685R	ADI	获取价格	Quad 16-/14-/12-Bit nanoDAC
AD5685RARUZ	ADI	获取价格	Quad, 16-/14-/12-Bit nanoDAC

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