AD5622WKSZ-1500RL7

更新时间： 2024-01-19 23:29:50

品牌	Logo	应用领域
亚德诺 - ADI		/
页数	文件大小	规格书
24页	560K
描述
2.7 V to 5.5 V, <100 uA, 8-/10-/12-Bit nanoDACs with

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AD5622WKSZ-1500RL7 数据手册

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AD5602/AD5612/AD5622

READ OPERATION

prepared to transmit data by pulling SDA low. Two bytes of data

are then read from the DAC, which are both acknowledged by

the master as shown in Figure 45, Figure 46, and Figure 47. A

stop condition follows.

When reading data back from the AD5602/AD5612/AD5622,

the user begins with a start command followed by an address

byte (R/ = 1), after which the DAC acknowledges that it is

SCL

R/W

PD1

PD0

SDA

START BY

ACK. BY

AD5602

ACK. BY

MASTER

FRAME 1

FRAME 2

SERIAL BUS ADDRESS BYTE

MOST SIGNIFICANT DATA BYTE FROM AD5602

SCL (CONTINUED)

SDA (CONTINUED)

NO ACK. BY STOP BY

MASTER MASTER

FRAME 3

LEAST SIGNIFICANT DATA BYTE FROM AD5602

Figure 45. AD5602 Read Sequence

SCL

R/W

PD1

PD0

SDA

START BY

ACK. BY

AD5612

ACK. BY

MASTER

FRAME 1

FRAME 2

SERIAL BUS ADDRESS BYTE

MOST SIGNIFICANT DATA BYTE FROM AD5612

SCL (CONTINUED)

SDA (CONTINUED)

NO ACK. BY STOP BY

MASTER MASTER

FRAME 3

LEAST SIGNIFICANT DATA BYTE FROM AD5612

Figure 46. AD5612 Read Sequence

SCL

R/W

PD1

PD0

D11

D10

SDA

START BY

ACK. BY

AD5622

ACK. BY

MASTER

FRAME 1

SERIAL BUS ADDRESS BYTE

FRAME 2

MOST SIGNIFICANT DATA BYTE FROM AD5622

SCL (CONTINUED)

SDA (CONTINUED)

NO ACK. BY STOP BY

MASTER MASTER

FRAME 3

LEAST SIGNIFICANT DATA BYTE FROM AD5622

Figure 47. AD5622 Read Sequence

Rev. B | Page 19 of 24

1...16 17 181920 21 22...24

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AD5622YKSZ-1500RL7	ADI	2.7 V to 5.5 V, <100 uA, 8-/10-/12-Bit nanoDACs with	获取价格
AD5622YKSZ-1REEL7	ADI	2.7 V to 5.5 V, <100 uA, 8-/10-/12-Bit nanoDACs with	获取价格
AD5622YKSZ-2	ADI	IC SERIAL INPUT LOADING, 6 us SETTLING TIME, 12-BIT DAC, PDSO6, LEAD FREE, PLASTIC, MO-203	获取价格
AD5622YKSZ-2500RL7	ADI	2.7 V to 5.5 V, <100 uA, 8-/10-/12-Bit nanoDACs with	获取价格