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AD5621AKS-REEL7 PDF预览

AD5621AKS-REEL7

更新时间: 2024-01-29 19:41:36
品牌 Logo 应用领域
亚德诺 - ADI 光电二极管转换器
页数 文件大小 规格书
17页 525K
描述
IC,D/A CONVERTER,SINGLE,12-BIT,CMOS,TSSOP,6PIN

AD5621AKS-REEL7 技术参数

生命周期:Obsolete包装说明:TSSOP, TSSOP6,.08
Reach Compliance Code:compliant风险等级:5.84
转换器类型:D/A CONVERTER输入位码:BINARY
JESD-30 代码:R-PDSO-G6最大线性误差 (EL):0.15%
位数:12功能数量:1
端子数量:6最高工作温度:125 °C
最低工作温度:-40 °C封装主体材料:PLASTIC/EPOXY
封装代码:TSSOP封装等效代码:TSSOP6,.08
封装形状:RECTANGULAR封装形式:SMALL OUTLINE, THIN PROFILE, SHRINK PITCH
电源:3/5 V认证状态:Not Qualified
子类别:Other Converters最大压摆率:0.1 mA
表面贴装:YES技术:CMOS
温度等级:AUTOMOTIVE端子形式:GULL WING
端子节距:0.635 mm端子位置:DUAL
Base Number Matches:1

AD5621AKS-REEL7 数据手册

 浏览型号AD5621AKS-REEL7的Datasheet PDF文件第4页浏览型号AD5621AKS-REEL7的Datasheet PDF文件第5页浏览型号AD5621AKS-REEL7的Datasheet PDF文件第6页浏览型号AD5621AKS-REEL7的Datasheet PDF文件第8页浏览型号AD5621AKS-REEL7的Datasheet PDF文件第9页浏览型号AD5621AKS-REEL7的Datasheet PDF文件第10页 
Preliminary Technical Data  
AD5601/AD5611/AD5621  
PIN CONFIGURATION AND FUNCTION DESCRIPTION  
1
2
3
6
5
4
V
SYNC  
SCLK  
OUT  
AD5641  
GND  
TOP VIEW  
(Not to Scale)  
V
DIN  
DD  
Figure 3. AD5601/AD5611/AD5621-1 SC70 (Top View)  
Table 4. Pin Function Descriptions  
Mnemonic  
Function  
VDD  
VOUT  
Power Supply Input. These parts can be operated from 2.7 V to 5.5 V, and VDD should be decoupled to GND.  
Analog Output Voltage from the DAC. The output amplifier has rail-to-rail operation.  
SYNC  
SYNC  
goes  
Level-Triggered Control Input (Active Low). This is the frame synchronization signal for the input data. When  
low, it enables the input shift register and data is transferred in on the falling edges of the following clocks. The DAC is  
SYNC  
updated following the 16th clock cycle unless  
is taken high before this edge in which case the rising edge of SYNC  
acts as an interrupt and the write sequence is ignored by the DAC.  
Serial Clock Input. Data is clocked into the input shift register on the falling edge of the serial clock input. Data can be  
transferred at rates up to 30 MHz.  
SCLK  
Serial Data Input. This device has a 16-bit shift register. Data is clocked into the register on the falling edge of the serial  
clock input.  
DIN  
GND  
Ground Reference Point for All Circuitry on the Part.  
Rev. PrB | Page 7 of 17  

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