Datasheet > AD5620CRM-3REEL7

AD5620CRM-3REEL7

更新时间： 2024-02-04 03:32:19

品牌	Logo	应用领域
亚德诺 - ADI		/
页数	文件大小	规格书
24页	554K
描述
Single, 12-/14-/16-Bit nanoDAC with 5 ppm/C On-Chip Reference in SOT-23

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AD5620CRM-3REEL7 数据手册

浏览型号AD5620CRM-3REEL7的Datasheet PDF文件第10页

AD5620/AD5640/AD5660

TIMING CHARACTERISTICS

All input signals are specified with tr = tf = 1 ns/V (10% to 90% of V_DD) and timed from a voltage level of (V_IL+ V_IH)/2. See Figure 2.

_DD= 2.7 V to 5.5 V; all specifications T_MINto T_MAX, unless otherwise noted.

Table 3.

Limit at T_MIN, T_MAX

V_DD= 3.6 V to 5.5 V

Parameter

V_DD= 2.7 V to 3.6 V

Unit

Conditions/Comments

SCLK cycle time

SCLK high time

SCLK low time

SYNC to SCLK falling edge set-up time

Data set-up time

t₁

ns min

t₂

t₃

t₄

t₅

t₆

t₇

t_±

t₉

t₁₀

4.5

Data hold time

SCLK falling edge to SYNC rising edge

Minimum SYNC high time

SYNC rising edge to SCLK fall ignore

SCLK falling edge to SYNC fall ignore

¹Maximum SCLK frequency is 30 MHz at V_DD= 3.6 V to 5.5 V and 20 MHz at V_DD= 2.7 V to 3.6 V.

t₁₀

t₁

t₉

SCLK

t₂

t₈

t₃

t₇

t₄

SYNC

DIN

t₆

t₅

MSB

LSB

LSB = DB0

MSB = DB23 FOR AD5660;

MSB = DB15 FOR AD5620/AD5640

Figure 2. Serial Write Operation

Rev. A | Page 7 of 24

1...4 5 678 9 10...24

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AD5620CRM-3REEL7 替代型号

型号	品牌	替代类型	描述	数据表
AD5620CRM-2REEL7	ADI	完全替代	Single, 12-/14-/16-Bit nanoDAC with 5 ppm/C On-Chip Reference in SOT-23
AD5620CRM-2	ADI	完全替代	Single, 12-/14-/16-Bit nanoDAC with 5 ppm/C On-Chip Reference in SOT-23
AD5620CRM-1	ADI	完全替代	Single, 12-/14-/16-Bit nanoDAC with 5 ppm/C On-Chip Reference in SOT-23

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