Preliminary Technical Data
AD5601/AD5611/AD5621
PIN CONFIGURATION AND FUNCTION DESCRIPTION
1
2
3
6
5
4
V
SYNC
SCLK
OUT
AD5641
GND
TOP VIEW
(Not to Scale)
V
DIN
DD
Figure 3. AD5601/AD5611/AD5621-1 SC70 (Top View)
Table 4. Pin Function Descriptions
Mnemonic
Function
VDD
VOUT
Power Supply Input. These parts can be operated from 2.7 V to 5.5 V, and VDD should be decoupled to GND.
Analog Output Voltage from the DAC. The output amplifier has rail-to-rail operation.
SYNC
SYNC
goes
Level-Triggered Control Input (Active Low). This is the frame synchronization signal for the input data. When
low, it enables the input shift register and data is transferred in on the falling edges of the following clocks. The DAC is
SYNC
updated following the 16th clock cycle unless
is taken high before this edge in which case the rising edge of SYNC
acts as an interrupt and the write sequence is ignored by the DAC.
Serial Clock Input. Data is clocked into the input shift register on the falling edge of the serial clock input. Data can be
transferred at rates up to 30 MHz.
SCLK
Serial Data Input. This device has a 16-bit shift register. Data is clocked into the register on the falling edge of the serial
clock input.
DIN
GND
Ground Reference Point for All Circuitry on the Part.
Rev. PrB | Page 7 of 17