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AD5611AKS-REEL7 PDF预览

AD5611AKS-REEL7

更新时间: 2024-02-28 18:31:58
品牌 Logo 应用领域
亚德诺 - ADI /
页数 文件大小 规格书
17页 525K
描述
IC,D/A CONVERTER,SINGLE,10-BIT,CMOS,TSSOP,6PIN

AD5611AKS-REEL7 数据手册

 浏览型号AD5611AKS-REEL7的Datasheet PDF文件第4页浏览型号AD5611AKS-REEL7的Datasheet PDF文件第5页浏览型号AD5611AKS-REEL7的Datasheet PDF文件第6页浏览型号AD5611AKS-REEL7的Datasheet PDF文件第8页浏览型号AD5611AKS-REEL7的Datasheet PDF文件第9页浏览型号AD5611AKS-REEL7的Datasheet PDF文件第10页 
Preliminary Technical Data  
AD5601/AD5611/AD5621  
PIN CONFIGURATION AND FUNCTION DESCRIPTION  
1
2
3
6
5
4
V
SYNC  
SCLK  
OUT  
AD5641  
GND  
TOP VIEW  
(Not to Scale)  
V
DIN  
DD  
Figure 3. AD5601/AD5611/AD5621-1 SC70 (Top View)  
Table 4. Pin Function Descriptions  
Mnemonic  
Function  
VDD  
VOUT  
Power Supply Input. These parts can be operated from 2.7 V to 5.5 V, and VDD should be decoupled to GND.  
Analog Output Voltage from the DAC. The output amplifier has rail-to-rail operation.  
SYNC  
SYNC  
goes  
Level-Triggered Control Input (Active Low). This is the frame synchronization signal for the input data. When  
low, it enables the input shift register and data is transferred in on the falling edges of the following clocks. The DAC is  
SYNC  
updated following the 16th clock cycle unless  
is taken high before this edge in which case the rising edge of SYNC  
acts as an interrupt and the write sequence is ignored by the DAC.  
Serial Clock Input. Data is clocked into the input shift register on the falling edge of the serial clock input. Data can be  
transferred at rates up to 30 MHz.  
SCLK  
Serial Data Input. This device has a 16-bit shift register. Data is clocked into the register on the falling edge of the serial  
clock input.  
DIN  
GND  
Ground Reference Point for All Circuitry on the Part.  
Rev. PrB | Page 7 of 17  

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