Quad, Current-Output,
Serial-Input 16-/14-Bit DACs
Data Sheet
AD5544/AD5554
FEATURES
FUNCTIONAL BLOCK DIAGRAM
VREFA B C D
AD5544: 16-bit resolution
INL of 1 LSB (B Grade)
AD5554: 14-bit resolution
INL of 0.5 LSB (B Grade)
2 mA full-scale current 20%, with VREF
0.9 µs settling time to 0.1%
12 MHz multiplying bandwidth
Midscale glitch of −1 nV-sec
Midscale or zero-scale reset
4 separate, 4-quadrant multiplying reference inputs
SPI-compatible, 3-wire interface
Double-buffered registers enable
Simultaneous multichannel change
Internal power-on reset
VDD
RFB
D0
D1
D2
D3
D4
D5
D6
D7
D8
A
SDI
INPUT
REGISTER
DAC A
REGISTER
IOUT
AGND
FBB
A
DAC A
R
R
R
R
R
R
R
R
A
= 10 V
R
INPUT
REGISTER
DAC B
REGISTER
16
D9
IOUT
B
DAC B
DAC C
DAC D
D10
D11
D12
D13
D14
D15
A0
AGND
B
RFBC
INPUT
REGISTER
DAC C
REGISTER
IOUT
C
SDO
A1
AGND
C
CS
RFBD
CLK
EN
INPUT
REGISTER
DAC D
REGISTER
IOUT
D
DAC
A
B
C
D
AGND
D
2:4
Temperature range: −40°C to +125°C
Compact 28-lead SSOP and 32-lead LFCSP
AD5544
POWER-ON
RESET
DECODE
AGND
F
DGND
RS
MSB
LDAC
VSS
APPLICATIONS
Figure 1.
Automatic test equipment
Instrumentation
Digitally controlled calibration
The AD5544 is packaged in the compact 28-lead SSOP and 32-
lead LFCSP. The AD5554 is packed in the compact 28-lead SSOP.
GENERAL DESCRIPTION
The AD5544/AD5554 quad, 16-/14-bit, current output, digital-
to-analog converters (DACs) are designed to operate from a
2.7 V to 5.5 V supply range.
The EV-AD5544/45SDZ is available for evaluating DAC perfor-
mance. For more information, see the UG-285 evaluation board
user guide.
The applied external reference input voltage (VREFx) determines
the full-scale output current. Integrated feedback resistors (RFB)
provide temperature-tracking, full-scale voltage outputs when
combined with an external I-to-V precision amplifier.
0.7
0.6
0.5
0.4
0.3
0.2
0.1
0
A double-buffered serial data interface offers high speed, 3-wire,
SPI- and microcontroller-compatible inputs using serial data in
CS
(SDI), a chip select ( ), and clock (CLK) signals. In addition,
a serial data out pin (SDO) allows for daisy-chaining when multiple
packages are used. A common, level-sensitive, load DAC strobe
LDAC
(
) input allows the simultaneous update of all DAC outputs
from previously loaded input registers. Additionally, an internal
power-on reset forces the output voltage to 0 at system turn-on.
–0.1
–0.2
RS
The MSB pin allows system reset assertion ( ) to force all registers
0
10,000 20,000 30,000 40,000 50,000 60,000 70,000
CODE
to zero code when MSB = 0 or to half-scale code when MSB = 1.
Figure 2. AD5544 INL vs. Code Plot (TA = 25°C)
Rev. G
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